Configurable non-volatile logic structure for characterizing an integrated circuit device
View Patent ↗An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.
1. An integrated circuit (IC) device, comprising:
a semiconductor substrate;
a plurality of device layers formed over the substrate; and
a plurality of multi-level revision (MLR) group structures, each having an output to generate a corresponding one of a plurality of bits of a revision code and comprising:
a plurality of MLR cells each extending through the device layers and having an output for generating a corresponding output signal; and
a parity circuit having a plurality of inputs each coupled to the output of a corresponding MLR cell in the MLR group structure, and having an output to generate the corresponding bit of the revision code.
2. The IC device of claim 1 , wherein the MLR cells do not consume static DC power.
3. The IC device of claim 1 , wherein each device layer is assigned to one MLR cell in each of the MLR group structures.
4. The IC device of claim 1 , wherein for each MLR group structure, the MLR cells are assigned to different device layers.
5. The IC device of claim 1 , wherein the revision code indicates design revisions in any of the device layers.
6. The IC device of claim 5 , wherein the revision codes are assigned to the design revisions in a non-sequential manner.
7. The IC device of claim 1 , wherein for each MLR group structure, the logic state of the corresponding bit of the revision code is controllable by anyone of the MLR cell output signals in the MLR group structure.
8. The IC device of claim 1 , wherein each bit of the revision code indicates a parity of the MLR cell output signals generated in the corresponding MLR group structure.
9. The IC device of claim 1 , wherein each parity circuit performs an exclusive-OR type logical combination of the MLR cell output signals within the corresponding MLR group structure.
10. The IC device of claim 1 , wherein each parity circuit is implemented by a number of transistors formed in the substrate, and the output of each MLR cell of the corresponding MLR group structure is coupled to a gate of one or more of the transistors.
11. The IC device of claim 10 , wherein each MLR cell includes a first continuity stack extending from the gate of the transistor and a first supply voltage provided on a top layer of the device, and includes a second continuity stack extending from the gate of the transistor and a second supply voltage provided on the top layer of the device.
12. The IC device of claim 1 , wherein each MLR cell comprises:
a first switching element coupled between the cell output and a first supply voltage; and
a second switching element coupled between the cell output and a second supply voltage.
13. The IC device of claim 12 , wherein:
the first switching element comprises a first continuity stack formed by a series connection of first continuity elements extending through all the device layers; and
the second switching element comprises a second continuity stack formed by a series connection of second continuity elements extending through all the device layers.
14. The IC device of claim 13 , wherein each device layer includes a corresponding pair of the first and second continuity elements.
15. The IC device of claim 13 , wherein:
in a first state, the first continuity elements electrically connect the cell output to the first supply voltage and the second continuity elements electrically isolate the cell output from the second supply voltage; and
in a second state, the second continuity elements electrically connect the cell output to the second supply voltage and the first continuity elements electrically isolate the cell output from the first supply voltage.
16. An integrated circuit (IC) device including a number of multi-level revision (MLR) structures to generate a revision code, each MLR group structure comprising:
a plurality of MLR cells each extending through a plurality of layers of the device and each having an output selectively connected either to a supply voltage or to ground potential; and
a parity circuit having a plurality of inputs each coupled to the output of a corresponding MLR cell in the MLR group structure, and having an output to generate a corresponding bit of the revision code.
17. The IC device of claim 16 , wherein the MLR cells do not consume static DC power.
18. The IC device of claim 16 , wherein the revision code indicates design revisions in any of the device layers.
19. The IC device of claim 16 , wherein the revision codes are assigned to the design revisions in a non-sequential manner.
20. The IC device of claim 16 , wherein for each MLR group structure, the logic state of the corresponding bit of the revision code is controllable by any one of the MLR cell output signals in the MLR group structure.
21. The IC device of claim 16 , wherein each bit of the revision code indicates a parity of the MLR cell output signals generated in the corresponding MLR group structure.
22. The IC device of claim 16 , wherein each parity circuit performs an exclusive-OR type logical combination of the MLR cell output signals within the corresponding MLR group structure.
23. The IC device of claim 16 , wherein each MLR cell comprises:
a first switching element coupled between the cell output and the supply voltage; and
a second switching element coupled between the cell output and ground potential.
24. The IC device of claim 23 , wherein:
the first switching element comprises a first continuity stack formed by a series connection of first continuity elements extending through all the device layers; and
the second switching element comprises a second continuity stack formed by a series connection of second continuity elements extending through all the device layers.
25. The IC device of claim 24 , wherein each device layer includes a corresponding pair of the first and second continuity elements.
26. The IC device of claim 24 , wherein:
in a first state, the first continuity elements electrically connect the MLR cell output to the supply voltage and the second continuity elements electrically isolate the MLR cell output from ground potential; and
in a second state, the second continuity elements electrically connect the MLR cell output to ground potential and the first continuity elements electrically isolate the MLR cell output from the supply voltage.