CMOS Compatible Single-Poly Non-Volatile Memory
The present invention teaches a single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. The single-poly non-volatile memory cell in accordance with the present invention comprises a program transistor with a program terminal; a sensing transistor with a sensing terminal; and an erase transistor with an erase terminal, wherein the sensing transistor shares a floating gate with the program transistor and the erase transistor. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided.
1 . A single-poly non-volatile memory cell comprising:
a program transistor with a program terminal;
a sensing transistor with a sensing terminal; and
an erase transistor with an erase terminal,
wherein the sensing transistor shares a floating gate with the program transistor and the erase transistor.
2 . The single-poly non-volatile memory cell as recited in claim 1 , wherein the gate area of the erase transistor is much smaller than that of the program transistor and that of the sensing transistor, respectively.
3 . The single-poly non-volatile memory cell as recited in claim 1 , wherein the program transistor, the sensing transistor and the erase transistor are PMOSFETs.
4 . The single-poly non-volatile memory cell as recited in claim 1 , wherein each of the program transistor, the sensing transistor and the erase transistor reside in three separate NWELLs.
5 . The single-poly non-volatile memory cell as recited in claim 1 , wherein the program transistor, the sensing transistor and the erase transistor have a substantially same gate oxide thickness in the range of 60-80 Å.
6 . The single-poly non-volatile memory cell as recited in claim 1 , wherein the potential on the shared floating gate is capacitively coupled from the program terminal, the erase terminal, and the sensing terminal.
7 . The single-poly non-volatile memory cell as recited in claim 1 , wherein the single-poly non-volatile memory cell is constructed with single poly-silicon.
8 . A single-poly non-volatile storage device, comprising:
a plurality of cells, each cell comprising:
a program transistor with a program terminal,
a sensing transistor with a sensing terminal, and
an erase transistor with an erase terminal,
wherein the sensing transistor shares a floating gate with the program transistor and the erase transistor.
9 . The single-poly non-volatile memory device as recited in claim 8 , wherein the gate area of the erase transistor is much smaller than that of the program transistor and that of the sensing transistor, respectively.
10 . The single-poly non-volatile memory device as recited in claim 8 , wherein the program transistor, the sensing transistor and the erase transistor are PMOSFETs.
11 . The single-poly non-volatile memory device as recited in claim 8 , wherein the program transistor, the sensing transistor and the erase transistor reside on three separate NWELLs.
12 . The single-poly non-volatile memory device as recited in claim 8 , wherein the program transistor, the sensing transistor and the erase transistor have the same gate oxide thickness in the range of 60-80 Å.
13 . The single-poly non-volatile memory device as recited in claim 8 , wherein the potential on the shared floating gate is capacitively coupled to the program terminal, the erase terminal, and the sensing terminal.
14 . The single-poly non-volatile memory device as recited in claim 8 , wherein each of the cells is constructed with single poly-silicon.
15 . The single-poly non-volatile memory device as recited in claim 8 , further comprising:
a program mechanism;
an erase mechanism; and
a read mechanism.
16 . The single-poly non-volatile memory device as recited in claim 15 , wherein the program mechanism functions by applying a first voltage on the program terminal, wherein the first voltage is not higher than 5V.
17 . The single-poly non-volatile memory device as recited in claim 15 , wherein the erase mechanism functions by applying a second voltage on the erase terminal, wherein the second voltage is not higher than 7V.
18 . The single-poly non-volatile memory device as recited in claim 15 , wherein the read mechanism functions without any external high voltage supply.
19 . The single-poly non-volatile memory device as recited in claim 15 , wherein the program mechanism functions by Channel Hot Electron (CHE) Injection.
20 . The single-poly non-volatile memory device as recited in claim 15 , wherein the erase mechanism functions by Fowler-Nordheim (FN) Tunneling.