Method of fabricating flash memory device using sidewall process
View Patent ↗A method of fabricating a flash memory device includes depositing and etching an insulating layer on a substrate having STI structures, depositing a first polysilicon layer over the insulating layer and the substrate, etching the first polysilicon layer to form floating gates and removing the insulating layer. The method also includes forming a first photoresist pattern, performing a first ion implantation using the first photoresist pattern to form first source/drain regions in the substrate and adjacent to the floating gate, removing the first photoresist pattern, depositing an ONO layer on the resulting structure, depositing a second polysilicon layer over the ONO layer, and etching the second polysilicon layer to form a control gate and at least one select gate. The method concludes by forming a second photoresist pattern and performing a second ion implantation using the second photoresist pattern to form second source/drain regions in the substrate and adjacent to the select gate.
1. A Method of fabricating a flash memory device using a sidewall process comprising:
depositing an insulating layer on a substrate;
forming at least one trench in the insulating layer by etching the insulating layer;
depositing a first polysilicon layer over and in said at least one trench;
forming floating gates on side surfaces of the insulating layer by etching the first polysilicon layer;
removing the insulating layer;
forming a first photoresist pattern over the substrate;
forming first source/drain regions in the substrate adjacent to the floating gate by a first ion implantation using the first photoresist pattern as a mask;
removing the first photoresist pattern
depositing an oxide-nitride-oxide (ONO) layer over the substrate;
depositing a second polysilicon layer over the ONO layer;
forming a control gate and at least one select gate by etching the second polysilicon layer;
forming a second photoresist pattern over the control gate and the select gate; and then
forming second source/drain regions in the substrate adjacent to the select gate by a second ion implantation using the second photoresist pattern as a mask.
2. The method of claim 1 , wherein the ONO layer comprises a first oxide layer with a thickness between about 50 Å and about 100 Å, a nitride layer with a thickness between about 50 Å and about 100 Å, and a second oxide layer with a thickness between about 300 Å and about 400 Å.
3. The method of claim 1 , wherein the second polysilicon layer has a thickness between about 1500 Å and about 2500 Å.
4. The method of claim 1 , wherein the control gate and the select gate are formed simultaneously during the etching of the second polysilicon layer.
5. The method of claim 1 , wherein the first ion implantation is performed after the floating gates are formed.
6. The method of claim 1 , wherein the first polysilicon layer is etched to form polysilicon sidewalls that serve as the floating gates on side surfaces of the trench.
7. The method of claim 1 , wherein the insulating layer has a thickness between about 2000 Å and about 3000 Å.
8. The method of claim 1 , wherein the first polysilicon layer has a thickness between about 4000 Å and about 6000 Å.
9. The method of claim 1 , wherein the first polysilicon layer is etched without a mask pattern to form the floating gates.
10. The method of claim 1 , wherein the insulating layer is removed by wet-etching after formation of the floating gates.