Nano-enabled memory devices and anisotropic charge carrying arrays
Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
1 . A memory device, comprising:
a substrate;
a source region of said substrate;
a drain region of said substrate;
a channel region between said source and drain regions;
a charge storage layer comprising a population of nanoelements above said channel region, said nanoelements made from a metal material;
a first dielectric layer deposited between said substrate and said charge storage layer;
a gate contact formed above or below said charge storage layer, said gate contact made from at least one metal selected from the group comprising W/TiN, TiN, Mo, TaN, and TaSi x N; and
a second dielectric layer deposited between said charge storage layer and said gate contact.
2 . The memory device of claim 1 , wherein said population of nanoelements includes a plurality of metal nanoparticles.
3 . The memory device of claim 2 , wherein each nanoelement comprises:
a metal core, and
a shell that surrounds said core.
4 . The memory device of claim 3 , wherein said shell is an oxidized layer of each nanoelement.
5 . The memory device of claim 1 , wherein said metal nanoelements are made from ruthenium or palladium.
6 . The memory device of claim 1 , wherein said metal nanoelements are made from a metal selected from the group comprising gold, palladium, iridium, platinum, ruthenium, cobalt, iron platinum alloy, and nickel.
7 . The memory device of claim 1 , further comprising a barrier layer deposited or formed in direct contact with said first dielectric layer and adjacent to said charge storage layer.
8 . The memory device of claim 7 , wherein the barrier layer comprises a nitrogen containing compound.
9 . The memory device of claim 8 , wherein the nitrogen containing compound comprises silicon nitride.
10 . The memory device of claim 8 , wherein the nitrogen containing compound comprises silicon oxynitride.
11 . The memory device of claim 7 , wherein the barrier layer comprises alumina.
12 . The memory device of claim 1 , wherein said gate contact comprises TaN or TiN.