IP Library Granted Patent US 8,093,102
Granted Patent B2
US 8,093,102 · App. 11/770,295 · Granted Jan 10, 2012

Process of forming an electronic device including a plurality of singulated die

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Quick Facts
Patent No.
US 8,093,102
App. No.
11/770,295
Granted
Jan 10, 2012
Kind
B2
Abstract

An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die.

Claims (56)

1. A process of forming an electronic device comprising:

attaching a first substrate to a first handling substrate, wherein the first substrate includes a bulk semiconductor material, a first plurality of die locations including a first die location including a first terminal at a first front side surface of the first die location, and, after attaching the first substrate, the first front side surface is adjacent to the first handling substrate;

removing a portion of the first substrate after attaching the first substrate to expose a first back side surface, wherein the first back side surface is separated from a first front side surface by a first thickness;

forming a first through via at the first die location;

forming a first electrical connection between a second terminal at a second front side surface of a second die and the first terminal of the first die, wherein:

forming the first electrical connection includes electrically connecting the second terminal and the first through via to each other;

the second die is a singulated die during formation of the first electrical connection;

the second die includes a second back side surface spaced apart from a second front side surface by a second thickness; and

the first thickness is less than half the second thickness;

singulating the first die from the first substrate while the first handling substrate is attached to the first substrate; and

removing the first handling substrate after singulating the first die from the first substrate.

2. The process of claim 1 , wherein forming the first electrical connection between the first terminal and the second terminal further includes orienting the second die such that the second front side surface and the first back side surface are front-to-back with respect to each other.

3. The process of claim 1 , wherein:

forming the first electrical connection further comprises forming a second electrical connection between another second terminal at the second front side surface of the second die and another first terminal at the first back side surface of the first die, wherein the first and second electrical connections are spaced apart from side edges of the first and second die; and

after singulating the first die, a void is disposed between and immediately adjacent to the first and second electrical connections along the first front side surface of the first substrate and the second back side surface of the second substrate.

4. The process of claim 1 , wherein after singulating the first die, the second die has the second thickness.

5. The process of claim 1 , wherein:

prior to attaching the first substrate to the first handling substrate, a first transistor lies at the first front side surface; and

prior to forming the first electrical connection between the second terminal at the second front side surface of the second die and the first terminal of the first die, a second transistor lies at the second front side surface.

6. The process of claim 1 , wherein:

removing a portion of the first substrate comprises removing only a portion of a bulk semiconductor material of the first substrate to leave a remaining portion of the bulk semiconductor material, and after removing the portion of the first substrate, the first thickness is less than approximately 90 microns; and

forming an opening through only a portion of the first thickness of the first substrate, wherein the opening extends through the remaining portion of the bulk semiconductor material.

7. The process of claim 1 , further including:

after removing the first handling substrate, attaching a third substrate to a second handling substrate, wherein the third substrate includes a third plurality of die including a third die location, a third terminal lies at a third front side surface of the third die location;

removing a portion of a third substrate to expose a third back side surface, wherein after removing the portion of the third substrate, the third back side surface is separated from a third front side surface by a third thickness;

forming a second through via at the third die location;

forming a second electrical connection between the second terminal and the third terminal wherein forming the second electrical connection includes electrically connecting the second terminal and the second through via at the third die location to each other; and

removing the second handling substrate, after forming the second electrical connection between the second and third terminals.

8. The process of claim 7 , wherein the second thickness and the third thickness have substantially a same value.

9. A process of forming an electronic device comprising:

attaching a first substrate to a handling substrate wherein the first substrate includes a first plurality of die locations including a first die location from which a first die can be subsequently singulated, wherein:

the first die includes a first front side surface and a first back side surface;

a first terminal and a transistor component region of the first die lie at the first front side surface; and

the handling substrate is a rigid substrate;

forming a first through via that extends from the first terminal towards the first back surface and through a remaining thickness of the first die wherein the first through via is electrically connected to the first terminal; and

flowing solder to form a first electrical connection between a second terminal at a second front side surface of a second die and the first terminal, and a second electrical connection between another second terminal at the second front side surface of the second die and another first terminal at the front side of the first die, wherein forming the electrical connection includes orienting the second die such that the second front side surface and the first back side surface are adjacent to each other,

wherein after flowing the solder, a void is disposed between the first and second electrical connections along the first front side surface of the first substrate and the second back side surface of the second substrate.

10. The process of claim 9 , wherein flowing the solder includes electrically connecting the first through via and the second terminal to each other.

11. The process of claim 9 , further including:

singulating the first die from the first substrate after flowing the solder; and

removing the first die from the handling substrate.

12. The process of claim 11 , further including:

orienting the first die such that the first front side surface and a third back side surface of a third die location of a third substrate are front-to-back with respect to each other; and

electrically connecting the first terminal at the first front side surface and a third terminal at a third front side surface opposite the third back side surface of the third substrate after removing the handling substrate from the first die, wherein electrically connecting the first terminal includes electrically connecting a second through via in the third die and the first terminal at the first front side surface to each other.

13. The process of claim 12 , further including electrically connecting the second terminal of the second die and the third terminal of the third die, wherein electrically connecting the second terminal includes electrically connecting the second through via and the second terminal to each other.

14. The process of claim 12 , further including:

removing a portion of the third substrate wherein after removing the portion of the third substrate, the third substrate has a third thickness; and

singulating the third die from the third substrate after removing the portion of the third substrate, wherein after singulating the third die:

the second die has a second thickness; and

the third thickness less than half the second thickness.

15. The process of claim 14 , wherein after singulating the third die, the second die is thicker than the first die and the third die.

16. The process of claim 9 , further comprising removing a portion of the first substrate after attaching the first substrate to the handling substrate and before forming the first through via, wherein after removing the portion of the first substrate, a remaining portion of the first substrate has a thickness is less than approximately 90 microns.

17. The process of claim 9 , wherein flowing the solder is performed after forming the first through via.

18. The process of claim 9 , further comprising plating a conductive layer within first through via before flowing the solder.

19. The process of claim 1 , wherein the second thickness is in a range of approximately 200 microns to approximately 400 microns

20. The process of claim 1 , wherein forming the first electrical connection comprises plating a conductive layer.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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SECURITY AGREEMENT Recorded Nov 1, 2007
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2007
From: SOMANI, AJAY
To: FREESCALE SEMICONDUCTOR, INC.
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