Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
This invention generally relates to a process for suppressing oxygen precipitation in epitaxial silicon wafers having a heavily doped silicon substrate and a lightly N-doped silicon epitaxial layer by dissolving existing oxygen clusters and precipitates within the substrate. Furthermore, the formation of oxygen precipitates is prevented upon subsequent oxygen precipitation heat treatment.
1 . A process for preparing an epitaxial single crystal silicon wafer, the process comprising:
annealing a heavily doped single crystal silicon substrate at a temperature of at least 1150° C. to dissolve pre-existing oxygen precipitates, the heavily doped silicon substrate being the slice of an ingot grown by the Czochralski method having a front surface, a back surface, and a circumferential edge joining the front and back surfaces, and having a resistivity of less than 5 mΩ*cm;
depositing an N− silicon epitaxial layer on the front surface of the rapidly heated heavily doped silicon substrate to form the epitaxial silicon wafer, the epitaxial layer comprising an N-type dopant and having a resistivity of greater than about 10 mΩ*cm; and
cooling the heavily doped silicon substrate from the annealing temperature to room temperature, wherein (i) the atmosphere of the annealing step is controlled or (ii) the cooling rate is controlled during the cooling step to install a uniform concentration of vacancies in the heavily doped single crystal silicon substrate, the uniform concentration being insufficient to catalyze oxygen precipitation in an oxidation precipitation heat-treatment.
2 . The process of claim 1 wherein the cooling step is carried out before the depositing step.
3 . The process of claim 2 wherein the atmosphere in which the annealing step is carried out comprises oxygen.
4 . The process of claim 3 wherein the atmosphere comprises a partial pressure of oxygen of at least about 1000 ppma.
5 . The process of claim 2 wherein the cooling rate is no more than 20° C. per second from the annealing temperature to the temperature at which vacancies are practically immobile.
6 . The process of claim 2 wherein the cooling rate is no more than 5° C. per second from the annealing temperature to the temperature at which vacancies are practically immobile.
7 . The process of claim 1 wherein the annealing step and the depositing step are carried out in the same apparatus, the cooling step is carried out after the depositing step, and the cooling rate is no more than 20° C. per second from the annealing temperature to the temperature at which vacancies are practically immobile.
8 . The process of claim 1 wherein the annealing step and the depositing step are carried out in the same apparatus, the cooling step is carried out after the depositing step, and the cooling rate is no more than 5° C. per second from the annealing temperature to the temperature at which vacancies are practically immobile.
9 . The process of claim 2 wherein cooling the heavily doped silicon substrate comprises cooling at a cooling rate greater than 20° C. per second from the annealing temperature to a temperature of less than about 1150° C. but greater than about 950° C., and then holding the substrate within this temperature range for at least about 2 seconds.
10 . The process of claim 9 wherein the heavily doped silicon substrate is cooled to a temperature of about 950° C., at which it is held for at least about 2 minutes.
11 . The process of claim 1 wherein the heavily doped silicon substrate comprises an N-type dopant.
12 . The process of claim 11 wherein the heavily doped silicon substrate comprises a dopant selected from the group consisting of P, As, and combinations thereof.
13 . The process of claim 1 wherein the heavily doped silicon substrate comprises a P-type dopant.
14 . The process of claim 13 wherein the heavily doped silicon substrate comprises a dopant selected from the group consisting of B, Al, Ga, and combinations thereof.
15 . The process of claim 1 wherein the N− silicon epitaxial layer is deposited to a thickness of at least about 5 cm.
16 . The process of claim 1 further comprising depositing a layer of polysilicon on the back surface of the heavily doped single crystal silicon substrate before the annealing step.
17 . An epitaxial silicon wafer comprising:
a heavily doped single crystal silicon substrate that is a slice of an ingot grown by the Czochralski method having a front surface, a back surface, and a circumferential edge joining the front and back surfaces; having a resistivity of less than 5 mΩ*cm; and being substantially free of oxygen precipitate nuclei;
an N− silicon epitaxial layer on the front surface of the heavily doped silicon substrate forming the epitaxial silicon wafer, the epitaxial layer comprising an N-type dopant and having a resistivity of greater than about 10 mΩ*cm.
18 . The wafer of claim 17 wherein the heavily doped silicon substrate comprises an N-type dopant.
19 . The wafer of claim 18 wherein the heavily doped silicon substrate comprises a dopant selected from the group consisting of P, As, and combinations thereof.
20 . The wafer of claim 17 wherein the heavily doped silicon substrate comprises a P-type dopant.
21 . The wafer of claim 20 wherein the heavily doped silicon substrate comprises a dopant selected from the group consisting of B, Al, Ga, and combinations thereof.
22 . The wafer of claim 17 wherein the N− silicon epitaxial layer has a thickness of at least about 5 cm.
23 . The wafer of claim 17 wherein the epitaxial layer has a resistivity of between about 100 mΩ·cm and about 100 Ω·cm.
24 . The wafer of claim 17 wherein the heavily doped silicon substrate comprises a region having a substantially uniform concentration of oxygen interstitial atoms that extends radially from the center of the wafer to a distance that is within 15 microns of the surface of the wafer.
25 . The wafer of claim 24 wherein the substantially uniform region has a concentration of oxygen interstitial atoms with a variance of no more than about 50%.
26 . The wafer of claim 24 wherein the substantially uniform region has a concentration of oxygen interstitial atoms with a variance of no more than about 10%.