METHOD TO FORM A REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTIVITY-SWITCHING GROWN OXIDE
A method is described to form a rewriteable memory cell including a diode and an oxide layer, wherein the resistivity of the oxide layer can be reversibly switched. In preferred embodiments, the oxide layer is a grown oxide. The diode is preferably formed of polysilicon which has been crystallized in contact with a silicide which has a close lattice match to silicon. The silicide provides a crystallization template such that the polysilicon is large-grained with few defects, and thus relatively low-resistivity. In preferred embodiments, a monolithic three dimensional memory array can be formed, in which multiple memory levels of such rewriteable memory cells are monolithically formed vertically stacked above a substrate.
1 . A method for forming a rewriteable memory cell, the method comprising:
forming a vertically oriented diode; and
thermally growing an oxide layer,
wherein the diode and the grown oxide layer are disposed electrically in series between a first conductor and a second conductor,
wherein the memory cell comprises the diode and the grown oxide, and
wherein the grown oxide layer serves as a reversible switching element.
2 . The method of claim 1 wherein the diode is a semiconductor junction diode comprising silicon.
3 . The method of claim 2 wherein the diode is a p-i-n diode.
4 . The method of claim 2 wherein the step of forming the vertically oriented diode comprises:
depositing the silicon, wherein at least some of the silicon is amorphous;
forming a titanium or cobalt layer above the amorphous silicon;
annealing to form a titanium silicide layer or a cobalt silicide layer and crystallize the amorphous silicon in contact with the silicide layer.
5 . The method of claim 4 wherein the step of thermally growing the oxide layer comprises growing an oxide layer on the silicide layer by heating the exposed silicide layer in an oxygen-containing ambient.
6 . The method of claim 4 wherein the step of forming the vertically oriented diode comprises patterning the amorphous silicon in the form of a pillar.
7 . The method of claim 6 wherein the step of forming a silicide layer in contact with the amorphous silicon comprises:
depositing titanium or cobalt above the amorphous silicon;
reacting the titanium or cobalt with the amorphous silicon to form the silicide layer; and
etching to remove the unreacted titanium or cobalt.
8 . The method of claim 7 wherein an oxide or oxynitride layer is disposed between the amorphous silicon and the titanium or cobalt, and wherein the oxide or oxynitride layer is fully reduced during the reacting step.
9 . The method of claim 1 wherein the grown oxide layer has an initial resistivity,
wherein a first set pulse is applied between the first conductor and the second conductor, and
wherein, after application of the first set pulse, the grown oxide layer has a second resistivity, the second resistivity lower than the initial resistivity.
10 . The method of claim 9
wherein, after application of the first set pulse, a first reset pulse is applied between the first conductor and the second conductor, and
wherein, after application of the first reset pulse, the grown oxide layer has a third resistivity, the third resistivity higher than the second resistivity.
11 . The method of claim 10 wherein during application of the first set pulse the diode is under forward bias.
12 . The method of claim 11 wherein during application of the first reset pulse the diode is under reverse bias.
13 . The method of claim 1 wherein the grown oxide is silicon dioxide.
14 . A method for forming a monolithic three dimensional memory array, the method comprising:
a) monolithically forming a first memory level above a substrate by a method comprising:
i) forming a plurality of bottom conductors;
ii) forming a plurality of top conductors;
iii) forming a plurality of vertically oriented diodes; and
iv) growing a plurality of oxide layers,
wherein the first memory level comprises a first plurality of memory cells,
wherein each memory cell comprises one of the diodes and one of the grown oxide layers disposed electrically in series between one of the bottom conductors and one of the top conductors,
wherein, for each memory cell, the grown oxide layer serves as a reversible switching element; and
b) monolithically forming a second memory level above the first.
15 . The method of claim 14 wherein each of the diodes is a semiconductor junction diode comprising silicon.
16 . The method of claim 15 wherein each of the diodes is a p-i-n diode.
17 . The method of claim 15 wherein the step of forming the plurality of vertically oriented diodes comprises:
depositing the silicon, wherein at least some of the silicon is amorphous;
depositing titanium or cobalt in contact with the amorphous silicon;
annealing to form a plurality of titanium silicide layers or cobalt silicide layers and to crystallize the amorphous silicon in contact with the silicide layers.
18 . The method of claim 17 wherein the step of thermally growing the plurality of oxide layers comprises growing the plurality of oxide layers on the plurality of silicide layers by heating the exposed silicide layers in an oxygen-containing ambient.
19 . The method of claim 14 wherein the first memory level comprises a first memory cell, the first memory cell comprising a first grown oxide layer and a first diode disposed between a first bottom conductor and a first top conductor,
wherein the first grown oxide layer has an initial resistivity,
wherein a first set pulse is applied between the first top conductor and the first bottom conductor, and
wherein, after application of the first set pulse, the first grown oxide layer has a second resistivity, the second resistivity lower than the initial resistivity.
20 . The method of claim 19
wherein, after application of the first set pulse, a first reset pulse is applied between the first bottom conductor and the first top conductor, and
wherein, after application of the first reset pulse, the first grown oxide layer has a third resistivity, the third resistivity higher than the second resistivity.
21 . The method of claim 14 wherein the plurality of grown oxides comprise silicon dioxide.
22 . The method of claim 14 wherein the substrate comprises monocrystalline silicon.