Method for manufacturing a semiconductor device including a memory cell array area and peripheral circuit area

1. A method for manufacturing a semiconductor device comprising consecutively:

forming a doped silicon layer on a semiconductor substrate defining first, second, and third areas, said second area being disposed adjacent to said third area;

patterning a first portion of said doped silicon layer formed on said first area, to form a first gate electrode;

selectively implanting impurities into said first area of said semiconductor substrate, to form first source/drain regions associated with said first gate electrode;

patterning a second portion of said doped silicon layer formed on said second and third areas, to form a second gate electrode; and

selectively implanting impurities into said second and third areas of said semiconductor substrate, to form second source/drain regions associated with said second gate electrode, and further comprising:

diffusing impurities in said first source/drain regions by using a heat treatment between said steps of selectively implanting of impurities to form said first source/drain regions and selectively implanting of impurities to form said second source/drain regions.

2. The method according to claim 1 , wherein said forming of doped silicon layer includes depositing a non-doped polysilicon layer on said semiconductor substrate, implanting first-conductivity-type impurities into a part of said polysilicon layer to form said first and second portions of said doped silicon layer, and implanting second-conductivity-type impurities into another part of said polysilicon layer to form said third portion of said doped silicon layer.

3. The method according to claim 1 , further comprising, between said forming said doped silicon layer and said patterning said first portion, depositing a metal layer on said doped silicon layer, wherein said first and second gate electrodes includes said doped silicon layer and said metal layer.

4. The method according to claim 1 , wherein said patterning said first portion forms a separation slot dividing said doped silicon layer between said second area and said third area.

5. The method according to claim 4 , further comprising, between said patterning said first portion and said patterning said second portion, forming a sidewall protective film on a sidewall of said first gate electrode and a sidewall of said separation slot.

6. The method according to claim 5 , further comprising, between said forming the sidewall protective film and said patterning said second portion, forming a contact electrode in a gap between adjacent two of a plurality of said first gate electrode and in said separation slot, said contact electrode connecting to said semiconductor substrate.