Radiation-hardened programmable device
View Patent ↗A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.
1. A method of converting a soft SRAM memory into a radiation hardened read-only memory, the method comprising:
programming a data pattern into an SRAM memory;
irradiating a transistor in the SRAM memory having a gate biased at VDD to provide a voltage threshold shift at a typical total dosage of between 300K and 1 Meg RAD in order to burn the data pattern into memory.
2. The method of claim 1 further comprising shipping the irradiated and programmed SRAM memory to the customer.
3. A programmable key method comprising:
providing a plurality of key circuits;
writing a data pattern into a plurality of key circuits; and
irradiating a transistor in the key circuits having a gate biased at VDD to provide a voltage threshold shift at a typical total dosage of between 300K and 1 Meg RAD in order to burn the data pattern into the key circuits.
4. The method of claim 3 in which providing a plurality of key circuits comprises providing a plurality of circuits each including an N-channel transistor and a resistor coupled together in a source-follower amplifier configuration.
5. The method of claim 3 in which providing a plurality of key circuits comprises providing a plurality of circuits each including an N-channel transistor and a resistor coupled together in a common-source amplifier configuration.
6. The method of claim 3 in which providing a plurality of key circuits comprises providing a plurality of circuits each including an N-channel transistor and a P-channel transistor coupled together in a common-source amplifier configuration.