Semiconductor device
View Patent ↗A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.
1. A semiconductor device, comprising: a substrate having a first-type MOS transistor with a first conductivity type, an input/output (I/O) second-type MOS transistor with a second conductivity type, and a core second-type MOS transistor with the second conductivity type formed thereon, wherein the first conductivity type is different from the second conductivity type; a first stress layer disposed on the first-type MOS transistor and the I/O second-type MOS transistor but not the core second-type MOS transistor; and a second stress layer only disposed on the core second-type MOS transistor and the I/O second-type MOS transistor, wherein the I/O second-type MOS transistor is overlaid by the first stress layer and the second stress layer is different from the first stress layer.
2. The semiconductor device of claim 1 , wherein if the first-type MOS transistor is an N-channel MOS (NMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are P-channel MOS (PMOS) transistors, the first stress layer is a tensile stress layer and the second stress layer is a compressive stress layer.
3. The semiconductor device of claim 1 , wherein if the first-type MOS transistor is a P-channel MOS (PMOS) transistor and the I/O second-type MOS transistor and the core second-type MOS transistor are N-channel MOS (NMOS) transistors, the first stress layer is a compressive stress layer and the second stress layer is a tensile stress layer.
4. The semiconductor device of claim 1 , wherein the first stress layer is made of a material comprising silicon nitride.
5. The semiconductor device of claim 1 , wherein the second stress layer is made of a material comprising silicon nitride.