Method for producing chip packages, and chip package produced in this way

1. A method for producing chip packages comprising:

providing a semiconductor wafer comprising a plurality of semiconductor chips, the semiconductor chips having first connection pads; and thereafter

applying second connection pads on the semiconductor wafer, including electrically connecting second connection pads to the first connection pads;

separating the semiconductor wafer into individual semiconductor chips;

producing a reconstituted wafer from mold compound in which a plurality of the semiconductor chips are encapsulated;

applying third connection pads to the reconstituted wafer; and

electrically connecting at least some of the third connection pads to the second connection pads using a thin-film process technology.

2. The method of claim 1 , comprising:

separating the reconstituted wafer into individual chip packages.

3. The method of claim 1 , comprising:

populating a carrier device, which carries the later reconstituted wafer, with a plurality of semiconductor chips.

4. The method of claim 3 , comprising:

wherein the carrier device comprises an adhesive layer;

a plurality of semiconductor chips are brought by their active top side onto the top side of the adhesive layer; and

after the production of the reconstituted wafer, the adhesive layer is detached from the reconstituted wafer.

5. The method of claim 1 , wherein connecting second connection pads to the first connection pads comprises using a thin-film process technology.

6. The method of claim 1 , comprising:

forming a layer composed of dielectric above the reconstituted wafer;

forming vias in the layer composed of dielectric, wherein each via is respectively located above a second connection pad; and

applying metal lines which are in each case electrically connected to a second connection pad through one of the vias, wherein the area of the second connection pad in each case extends both beyond the area of the via, and beyond the area of the metal line in the contact region with the via.

7. The method of claim 6 , comprising wherein a width of the via in each case amounts to 30 to 70% of a width of the second connection pad.

8. The method of claim 1 , comprising:

forming a layer composed of dielectric above the reconstituted wafer;

forming vias in the layer composed of dielectric, wherein each via is respectively located above a second connection pad; and

applying metal lines which are in each case electrically connected to a second connection pad through one of the vias, wherein in each case the area of the metal line in the contact region with the via extends beyond the area of the second connection pad, and the area of the via is essentially congruent with the area of the second connection pad.

9. The method of claim 8 , comprising wherein the width of the metal line in the contact region in each case amounts to 130 to 200% of the width of the second connection pad.

10. The method of claim 1 , comprising wherein the second connection pads are in each case wider than the first connection pads.

11. The method of claim 1 , comprising wherein a pitch of the second connection pads is greater than the pitch of the first connection pads.

12. The method of claim 1 , comprising applying for each semiconductor chip the second connection pads substantially over the whole area over the chip area.

13. The method of claim 1 , comprising wherein the chip packages are fan-out wafer lever packages.

14. The method of claim 1 , wherein all second connection pads are located in an inner chip area which is surrounded by the first connection pads.

15. The method of claim 1 , further comprising:

applying solder balls on the third connection pads.

16. A method for producing chip packages comprising:

providing a semiconductor wafer comprising a plurality of semiconductor chips, the semiconductor chips having first connection pads;

applying a first layer of dielectric over the semiconductor wafer;

forming second connection pads on the first dielectric layer and electrically connecting second connection pads to the first connection pads through vias in the first dielectric layer;

separating the semiconductor wafer into individual semiconductor chips;

producing a reconstituted wafer from mold compound in which a plurality of the semiconductor chips are encapsulated;

applying a second layer of dielectric over the reconstituted wafer;

forming third connection pads on the second dielectric layer and electrically connecting at least some of the third connection pads to the second connection pads through vias in the second dielectric layer; and

separating the reconstituted wafer into individual chip packages.

17. The method of claim 16 , comprising:

applying solder balls on the third connection pads prior to separating the reconstituted wafer into individual chip packages.

18. The method of claim 16 , comprising:

contact-connecting a first subset of the first connection pads to the second connection pads before separating the semiconductor wafer; and

contact-connecting a second subset of first connection pads to third connection pads which have not been connected to second connection pads.

19. The method of claim 16 , wherein all second connection pads are located in an inner chip area which is surrounded by the first connection pads.

20. The method of claim 1 , further including:

applying a layer of dielectric over the reconstituted wafer; and

applying the third connection pads on the dielectric layer, wherein at least some of the third connection pads are connected to the second connection pads through vias in the dielectric.

21. The method of claim 20 , wherein the third connection pads are arranged both outside a chip area and within the chip area.