Semiconductor structure
View Patent ↗A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.
1. A semiconductor structure, comprising:
a substrate that has thereon a gate structure and a spacer on a sidewall of the gate structure and has therein a recess beside the spacer;
an S/D extension region in the substrate beside the gate structure;
an S/D region in the substrate-surrounding the recess, wherein the S/D region comprises a doped epitaxial layer on the substrate at the bottom of the recess;
a stress layer over the substrate, a part of the stress layer filled in the recess; and
a metal silicide layer between the S/D region and the stress layer, and between the gate structure and the stress layer.
2. The semiconductor structure of claim 1 , wherein the stress layer has a sufficient thickness to at least fill up the recess.
3. The semiconductor structure of claim 1 , wherein the stress layer is a compressive stress layer or a tensile stress layer.
4. The semiconductor structure of claim 1 , wherein the S/D region comprises an implanted region in the substrate at the bottom of the recess.
5. The semiconductor structure of claim 1 , wherein the doped epitaxial layer comprises doped SiGe or doped SiC.
6. A semiconductor structure, comprising:
a substrate;
a first MOS transistor of a first conductivity type on the substrate, comprising:
a first gate structure on the substrate;
a first spacer on a sidewall of the first gate structure, while the substrate has a recess therein beside the first spacer;
a first S/D extension region of the first conductivity type in the substrate beside the first gate structure; and
a first S/D region of the first conductivity type in the substrate surrounding the recess;
a second MOS transistor of a second conductivity type on the substrate, comprising:
a second gate structure on the substrate;
a second spacer on a sidewall of the second gate structure;
a second S/D extension region of the second conductivity type in the substrate beside the second gate structure; and
a second S/D region of the second conductivity type in the substrate beside the second spacer;
a first stress layer over the first MOS transistor, a part of the first stress layer filled in the recess; and
a second stress layer over the second MOS transistor, wherein the first conductivity type is P-type, the second conductivity type is N-type, the first stress layer is a compressive stress layer, the second stress layer is a tensile stress layer, the first S/D region comprises a P-doped SiGe layer on the substrate at the bottom of the recess, and the P-doped epitaxial layer comprises P-doped SiGe.
7. The semiconductor structure of claim 6 , further comprising a metal silicide layer on the first and the second S/D regions and the first and the second gate structures.
8. The semiconductor structure of claim 6 , wherein the first stress layer has a sufficient thickness to at least fill up the recess.
9. The semiconductor structure of claim 6 , wherein the first S/D region comprises an implanted region in the substrate at the bottom of the recess.
10. A semiconductor structure comprising:
a substrate;
a first MOS transistor of a first conductivity type on the substrate, comprising:
a first gate structure on the substrate:
a first spacer on a sidewall of the first gate structure, while the substrate has a recess therein beside the first spacer;
a first S/D extension region of the first conductivity type in the substrate beside the first gate structure; and
a first S/D region of the first conductivity type in the substrate surrounding the recess;
a second MOS transistor of a second conductivity type on the substrate, comprising:
a second gate structure on the substrate;
a second spacer on a sidewall of the second gate structure;
a second S/D extension region of the second conductivity type in the substrate beside the second gate structure; and
a second S/D region of the second conductivity type in the substrate beside the second spacer;
a first stress layer over the first MOS transistor, a part of the first stress layer filled in the recess; and
a second stress layer over the second MOS transistor, wherein the first conductivity type is N-type, the second conductivity type is P-type, the first stress layer is a tensile stress layer, the second stress layer is a compressive stress layer, the first S/D region comprises an N-doped epitaxial layer on the substrate at the bottom of the recess, and the N-doped epitaxial layer comprises N-doped SiC.
11. The semiconductor structure of claim 10 , further comprising a metal silicide layer on the first and the second S/D regions and the first and the second gate structures.
12. The semiconductor structure of claim 10 , wherein the first stress layer has a sufficient thickness to at least fill up the recess.
13. The semiconductor structure of claim 10 , wherein the first S/D region comprises an implanted region in the substrate at the bottom of the recess.