Method of fabricating back-illuminated imaging sensors using a bump bonding technique
View Patent ↗A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer; forming a plurality of bond pads substantially overlying the epitaxial layer; fabricating a dielectric layer substantially overlying the epitaxial layer and the at least one imaging component; providing a handle wafer; forming a plurality of conductive trenches in the handle wafer; forming a plurality of conductive bumps on a first surface of the handle wafer substantially underlying the conductive trenches; and bonding the plurality of conductive bumps to the plurality of bond pads.
1. A method for fabricating a semiconductor device, comprising the steps of:
providing a substrate comprising:
an insulator layer, and
an epitaxial layer substantially overlying the insulator layer;
forming a plurality of alignment keys substantially overlying the epitaxial layer by:
printing key patterns on a top portion of the epitaxial layer,
etching the underlying epitaxial layer below the key patterns using a trench etch process until the etched away silicon is stopped by the underlying insulator layer, and
filling the opened trenches with an electrically insulating material;
forming a plurality of bond pads substantially overlying the epitaxial layer;
fabricating a dielectric layer substantially overlying the epitaxial layer;
providing a handle wafer;
forming a plurality of conductive trenches in the handle wafer;
forming a plurality of conductive bumps on a first surface of the handle wafer substantially underlying the conductive trenches; and
bonding the plurality of conductive bumps to the plurality of bond pads.
2. The method of claim 1 , wherein the electrically insulating material is one of an oxide of silicon, silicon carbide, silicon nitride, and poly-silicon.
3. The method of claim 1 , wherein the step of forming a plurality of conductive trenches in the handle wafer further comprises the steps of:
etching vias in the handle wafer;
filling the vias with a conducting material; and
smoothing the first surface of the handle wafer.
4. The method of claim 3 , wherein the vias are filled with a conductive material using one of an electroplating and sputtering technique.
5. The method of claim 1 , further comprises the steps of:
forming a plurality of bond pads substantially overlying a second surface of the handle wafer; and
attaching a plurality of bond wires to the plurality of bond pads substantially overlying the second surface of the handle wafer.
6. The method of claim 5 , wherein said step of forming a plurality of bond pads substantially overlying the second surface of the handle wafer further comprises the steps of:
depositing a conductive material substantially on the second surface of the handle wafer; and
patterning and etching the conductive material to obtain the plurality of bond pads over the filled metal trenches.
7. The method of claim 6 , wherein the conductive material is made of a metal.
8. The method of claim 7 , wherein the metal is one of gold, tin, and wolfram.
9. The method of claim 1 , further comprising the step of fabricating at least one optical component substantially overlying the epitaxial layer and proximal to the insulating layer using the plurality of alignment keys as guides.
10. The method of claim 9 , wherein the step of fabricating at least one optical component includes the step of fabricating color filters and micro-lenses, in any combination.
11. The method of claim 9 , further comprising the step of forming a dielectric layer substantially overlying the epitaxial layer before said step of forming a plurality of bond pads substantially overlying the epitaxial layer.
12. The method of claim 11 , further comprising the step of forming a plurality of conductive bond pads substantially on the first surface of the handle wafer substantially underlying the filled conductive trenches before said step of bonding the plurality of metal bumps to the plurality of bond pads substantially overlying the epitaxial layer.
13. The method of claim 1 , wherein the handle wafer is fabricated from one of silicon, aluminum nitride, and ceramic.
14. The method of claim 1 , wherein the step of bonding the plurality of metal bumps to the plurality of bond pads at least partially overlying the imaging area further comprises the steps of applying a predetermined pressure and temperature to the substrate and the handle wafer.
15. The method of claim 1 , wherein resistivity of the epitaxial layer is controlled by the epitaxial profile.
16. The method of claim 1 , further comprising the step of fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer.
17. The method of claim 16 , wherein the at least one imaging component has an imaging area, and wherein at least one of the plurality of bond pads substantially overlying the epitaxial layer also at least partially overlies the imaging area.
18. The method of claim 16 , wherein the at least one imaging component includes at least one of CMOS imaging components, charge-coupled device (CCD) components, photodiodes, avalanche photodiodes, and phototransistors.
19. The method of claim 16 , wherein the step of fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer further comprises the steps of:
forming a second imaging component at least partially overlying and extending into the epitaxial layer, the at least one imaging component and the second imaging component being formed substantially between the alignment keys.