Method for forming salicide in semiconductor device
View Patent ↗Forming salicide in a semiconductor device includes the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region. Therefore, a non-salicide region and a salicide region can be formed selectively and simultaneously in a one-chip semiconductor device, so that the number of steps for a salicide forming process can be reduced.
1. A method for forming salicide in a semiconductor device, the method comprising the steps of:
(1) forming a first gate oxide film and a second gate oxide film in a non-salicide region and a salicide region of a silicon substrate, respectively, the first gate oxide film being thicker than the second gate oxide film;
(2) forming a conductive layer and a nitride based hard mask layer on an upper surface of a first resultant structure obtained through step (1), and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes respectively in the non-salicide region and the salicide region and simultaneously exposing an active region of the salicide region;
(3) forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure obtained through steps (1) to (2);
(4) selectively removing the spacer oxide film, thereby forming a spacer on one side of each of the gate electrodes and simultaneously exposing the active region of the salicide region;
(5) removing the hard mask layer remaining on upper surfaces of the gate electrodes in the non-salicide region and the salicide region; and
(6) forming a salicide film on the upper surfaces of the gate electrodes formed in the non-salicide region and the salicide region, and on the surface of the active region in the salicide region.
2. The method as claimed in claim 1 , wherein an etching process for the hard mask layer and the conductive layer includes first and second etching steps.
3. The method as claimed in claim 2 , wherein when the second etching step for the conductive layer is performed, activated plasma including Cl 2 /HBr/He—O 2 /Ar is used.
4. The method as claimed in claim 1 , wherein the hard mask layer has a thickness of 1˜500 Å.
5. The method as claimed in claim 1 , wherein etching gases used for etching the spacer oxide film and flow rates thereof are CHF 3 : 1˜200 sccm, CF 4 : 1˜200 sccm, O 2 : 0˜20 sccm, Ar: 1˜1000 sccm, C 4 F 8 : 1A˜50 sccm and N 2 : 0˜500 sccm.
6. The method as claimed in claim 1 , wherein an etching process of the hard mask layer is performed by a down flow method with using O 2 /CF 4 as etching gas.