IP Library Granted Patent US 7,867,828
Granted Patent B2
US 7,867,828 · App. 11/782,587 · Granted Jan 11, 2011

Method of fabricating a semiconductor device including forming an insulating layer with a hard sheet buried therein

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,867,828
App. No.
11/782,587
Granted
Jan 11, 2011
Kind
B2
Abstract

A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.

Claims (26)

1. A semiconductor device fabrication method comprising:

separately arranging, on an upper surface of a base plate, a plurality of semiconductor constituent bodies each having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate;

forming, on the upper surface of the base plate around each semiconductor constituent body, an insulating layer formation layer made of a material containing a resin selected from the group consisting of a semi-hardened thermosetting resin and liquid thermosetting resin, and placing, on an upper surface of the insulating layer formation layer, a hard sheet having a hole corresponding to each semiconductor constituent body;

performing heating and pressing to form an insulating layer on the base plate around each semiconductor constituent body by fully hardening the semi-hardened thermosetting resin or liquid thermosetting resin in the insulating layer formation layer, and to bury at least a portion of the hard sheet in the insulating layer;

forming an interconnection to be connected to the external connecting electrodes of each semiconductor constituent body; and

obtaining a plurality of semiconductor devices by cutting the hard sheet, insulating layer, and base plate between the semiconductor constituent bodies.

2. A semiconductor device fabrication method according to claim 1 , wherein the insulating layer formation layer is made of an insulating layer formation sheet which is semi-hardened and has a hole corresponding to each semiconductor constituent body.

3. A semiconductor device fabrication method according to claim 2 , wherein forming the insulating layer formation layer further comprises forming another insulating layer formation sheet on the hard sheet, and placing another hard sheet on the another insulating layer formation sheet.

4. A semiconductor device fabrication method according to claim 1 , wherein forming the insulating layer formation layer comprises coating a material containing the liquid thermosetting resin on the base plate around each semiconductor constituent body.

5. A semiconductor device fabrication method according to claim 1 , wherein the insulating layer formation layer is semi-hardened and integrally formed on a lower surface of the hard sheet.

6. A semiconductor device fabrication method according to claim 1 , wherein the hard sheet is made of substantially the same material as the base plate.

7. A semiconductor device fabrication method according to claim 1 , wherein the hard sheet has substantially the same thickness as the base plate.

8. A semiconductor device fabrication method according to claim 1 , wherein the base plate and hard sheet are made of a material containing at least a thermosetting resin, and are hardened before performing the heating and pressing.

9. A semiconductor device fabrication method according to claim 1 , wherein the base plate and hard sheet are formed of a substrate including an inorganic material.

10. A semiconductor device fabrication method according to claim 1 , wherein the hard sheet is made of substantially the same material as the insulating layer.

11. A semiconductor device fabrication method according to claim 1 , wherein the hard sheet is made of a material having substantially the same thermal expansion coefficient as the base plate.

12. A semiconductor device fabrication method according to claim 1 , wherein one of the base plate and hard sheet is made of a metal sheet, and the other is made of a material containing at least a thermosetting resin.

13. A semiconductor device fabrication method according to claim 12 , wherein the metal sheet is made of a material selected from the group comprising copper and stainless steel.

14. A semiconductor device fabrication method according to claim 1 , wherein the interconnection is an upper interconnection, and the semiconductor device fabrication method further comprises forming an upper insulating film on the hard sheet, and forming the upper interconnection on the upper insulating film.

15. A semiconductor device fabrication method according to claim 14 , wherein forming the upper insulating film on the hard sheet comprises forming a semi-hardened upper insulating film on the hard sheet, and fully hardening the semi-hardened upper insulating film by heating and pressing.

16. A semiconductor device fabrication method according to claim 15 , wherein the insulating layer and upper insulating film are simultaneously fully hardened by heating and pressing.

17. A semiconductor device fabrication method according to claim 15 , wherein at the same time the upper insulating film is fully hardened by heating and pressing, a lower insulating film made of substantially the same material as the upper insulating film is formed on a lower surface of the base plate.

18. A semiconductor device fabrication method according to claim 17 , wherein the insulating layer, upper insulating film, and lower insulating film are simultaneously fully hardened by heating and pressing.

19. A semiconductor device fabrication method according to claim 14 , further comprising forming an uppermost insulating film which covers a portion except for a connecting pad portion of the upper interconnection, and forming, on a lowermost surface of the base plate, a lowermost insulating film made of substantially the same material as the uppermost insulating film.

20. A semiconductor device fabrication method according to claim 19 , wherein the uppermost insulating film and lowermost insulating film are formed of a solder resist.

21. A semiconductor device fabrication method according to claim 19 , further comprising forming a solder ball on the connecting pad portion of upper interconnection.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2017
From: TERA PROBE, INC.
To: AOI ELECTRONICS CO., LTD.
Reel/Frame 041123/0931 →
MERGER Recorded Nov 30, 2016
From: TERAMIKROS, INC.
To: TERA PROBE, INC.
Reel/Frame 040769/0853 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2016
From: JOBETTO, HIROYASU
To: CASIO COMPUTER CO., LTD.
Reel/Frame 040413/0407 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2016
From: CASIO COMPUTER CO., LTD.
To: CASIO COMPUTER CO., LTD.; CMK CORPORATION
Reel/Frame 040413/0485 →
CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE'S ADDRESS ON REEL 027465, FRAME 0812 Recorded Jan 6, 2012
From: CASIO COMPUTER CO., LTD.
To: TERAMIKROS, INC.
Reel/Frame 027492/0449 →
CHANGE OF OWNERSHIP BY CORPORATE SEPARATION Recorded Jan 3, 2012
From: CASIO COMPUTER CO., LTD.
To: TERAMIKROS, INC.
Reel/Frame 027465/0812 →