IP Library Granted Patent US 7,721,422
Granted Patent B2
US 7,721,422 · App. 11/784,810 · Granted May 25, 2010

Methods of making microelectronic assemblies

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Quick Facts
Patent No.
US 7,721,422
App. No.
11/784,810
Granted
May 25, 2010
Kind
B2
Abstract

A method of making a microelectronic assembly includes providing a conductive metal layer having a first surface and a second surface, and etching the first surface of the conductive metal layer to form conductive protrusions, whereby after the etching step, the second surface of the conductive metal layer defines a substantially flat, continuous surface. The method includes juxtaposing a layer of an insulating material with tips of the conductive protrusions, and pressing the conductive protrusions through the layer of an insulating material so that the tips of the conductive protrusions are accessible at a first surface of the layer of an insulating material.

Claims (52)

1. A method of making a microelectronic assembly, said method comprising:

providing a conductive metal layer having a first surface and a second surface;

etching the first surface of said conductive metal layer to form conductive protrusions each having a respective tip, wherein after the etching step, the second surface of said conductive metal layer defines a substantially flat, continuous surface;

juxtaposing a layer of an insulating material with said tips of said conductive protrusions;

pressing said conductive protrusions completely through said layer of an insulating material so that said tips of said conductive protrusions protrude through said layer of an insulating material and are accessible at a first surface of said layer of an insulating material; and

heating said layer of an insulating material before the pressing step so as to soften said layer of an insulating material during the pressing step.

2. The method as claimed in claim 1 , further comprising after the pressing step, etching the second surface of said conductive metal layer to form conductive traces that are electrically interconnected with said conductive protrusions.

3. The method as claimed in claim 1 , further comprising cooling said layer of an insulating material after the pressing step to prevent curing of the layer of an insulating material.

4. The method as claimed in claim 1 , further comprising electrically interconnecting a microelectronic element with said conductive protrusions for forming a microelectronic package.

5. The method as claimed in claim 1 , further comprising electrically interconnecting said conductive protrusions with one or more conductive elements in a multilayer microelectronic assembly.

6. A method of making a microelectronic assembly, said method comprising:

etching the first surface of said conductive metal layer to form conductive protrusions each having a respective tip, wherein after the etching step, the second surface of said conductive metal layer defines a substantially flat, continuous surface;

juxtaposing a layer of an insulating material with said tips of said conductive protrusions;

pressing said conductive protrusions completely through said layer of an insulating material so that said tips of said conductive protrusions protrude through said layer of an insulating material and are accessible at a first surface of said layer of an insulating material, and

after the pressing step,

juxtaposing a conductive metal foil with said tips of said conductive protrusions accessible at the first surface of said layer of an insulating material, and

abutting said conductive metal foil against the first surface of said layer of an insulating material, wherein said conductive metal foil is in communication with said tips of said conductive protrusions.

7. The method as claimed in claim 6 , further comprising etching said conductive metal foil to form conductive traces electrically interconnected with said conductive protrusions.

8. A method of making a microelectronic assembly, said method comprising:

providing a conductive metal layer having a first surface and a second surface;

etching the first surface of said conductive metal layer to form conductive protrusions each having a respective tip, wherein after the etching step, the second surface of said conductive metal layer defines a substantially flat, continuous surface;

juxtaposing a layer of an insulating material with said tips of said conductive protrusions;

heating said layer of an insulating material to at least a temperature at which said layer of an insulating material softens;

while maintaining said layer of an insulating material at least at the temperature at which said layer of an insulating material softens, pressing said conductive protrusions completely through said layer of an insulating material so that said tips of said conductive protrusions protrude through said layer of an insulating material and are accessible at a first surface of said layer of an insulating material;

electrically interconnecting a microelectronic element with said conductive protrusions.

9. The method as claimed in claim 8 , further comprising, after the pressing step, etching the second surface of said conductive metal layer to form conductive traces that are electrically interconnected with said conductive protrusions.

10. The method as claimed in claim 8 , further comprising, after the pressing step, cooling said layer of an insulating material to prevent curing of the layer of an insulating material.

11. The method as claimed in claim 8 , further comprising electrically interconnecting said conductive protrusions with one or more conductive elements in a multilayer microelectronic structure.

12. The method as claimed in 8 , further comprising:

after the pressing step, juxtaposing a conductive metal foil with said tips of said conductive protrusions accessible at the first surface of said layer of an insulating material;

abutting said conductive metal foil against the first surface of said layer of an insulating material, wherein said conductive metal foil is in communication with said tips of said conductive protrusions.

13. The method as claimed in claim 12 , further comprising etching said conductive metal foil to form conductive traces electrically interconnected with said conductive protrusions.

14. A method of making a microelectronic assembly, said method comprising:

providing a three metal layer including a first metal layer, a second metal layer and a third metal layer;

removing portions of said first and second metal layers to form conductive protrusions formed of remaining portions of said first and second metal layers that overlie said third metal layer, wherein each said conductive protrusion has a respective tip remote from said third metal layer, and wherein after the removing step, a bottom surface of said third metal layer defines a substantially flat, continuous surface;

juxtaposing a layer of an insulating material with said tips of said conductive protrusions;

pressing said tips of said conductive protrusions completely through said layer of an insulating material so that said tips of said conductive protrusions protrude through said layer of an insulating material and are accessible at a first surface of said layer of an insulating material;

before the pressing step, heating said layer of an insulating material to a first temperature at which said layer of an insulating material softens; and

after the pressing step, cooling said layer of an insulating material to a second temperature that is less than the first temperature.

15. The method as claimed in claim 14 , further comprising after the pressing step, removing portions of said third metal layer to form conductive traces that are electrically interconnected with said conductive protrusions.

16. A method of making a microelectronic assembly, said method comprising:

providing a three metal layer including a first metal layer, a second metal layer and a third metal layer;

removing portions of said first and second metal layers to form conductive protrusions formed of remaining portions of said first and second metal layers that overlie said third metal layer, wherein each said conductive protrusion has a respective tip remote from said third metal layer, and wherein after the removing step, a bottom surface of said third metal layer defines a substantially flat, continuous surface;

juxtaposing a layer of an insulating material with said tips of said conductive protrusions;

pressing said tips of said conductive protrusions completely through said layer of an insulating material so that said tips of said conductive protrusions protrude through said layer of an insulating material and are accessible at a first surface of said layer of an insulating material; and

after the pressing step,

juxtaposing a conductive metal foil with said tips of said conductive protrusions accessible at the first surface of said layer of an insulating material, and

abutting said conductive metal foil against the first surface of said layer of an insulating material, wherein said conductive metal foil is electrically interconnected with said tips of said conductive protrusions.

17. The method as claimed in claim 16 , further comprising removing portions of said conductive metal foil fo form conductive trace electrically interconnected with said conductive protrusions.

18. The method as claimed in claim 17 , further comprising electrically interconnecting said conductive protrusions with a microelectronic structure having one or more layers.

19. The method as claimed in claim 17 , further comprising electrically interconnecting a microelectronic element with said conductive protrusions so as to form a microelectronic package.

20. The method as claimed in claim 19 , further comprising electrically interconnecting said microelectronic package with a microelectronic structure having one or more layers.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
MERGER Recorded Jan 30, 2012
From: TESSERA INTERCONNECT MATERIALS, INC.
To: INVENSAS CORPORATION
Reel/Frame 027622/0384 →
RE-RECORD TO CORRECT THE ADDRESS OF THE ASSIGNEE, PREVIOUSLY RECORDED ON REEL 023961 FRAME 0914. Recorded Apr 28, 2010
From: IIJIMA, TOMOO; OHSAWA, MASAYUKI
To: NORTH CORPORATION
Reel/Frame 024298/0981 →
CORRECTION TO REEL 023961 FRAME 0914 TO CORRECT ASSIGNEE'S ADDRESS Recorded Apr 27, 2010
From: IIJIMA, TOMOO; OHSAWA, MASAYUKI
To: NORTH CORPORATION
Reel/Frame 024298/0433 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2010
From: SOCKETSTRATE, INC.
To: TESSERA INTERCONNECT MATERIALS, INC.
Reel/Frame 023972/0956 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2010
From: NORTH CORPORATION
To: SOCKETSTRATE, INC.
Reel/Frame 023968/0619 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2010
From: IIJIMA, TOMOO; OHSAWA, MASAYUKI
To: NORTH CORPORATION
Reel/Frame 023961/0914 →