Semiconductor integrated circuit and a method of testing the same
View Patent ↗A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
1. A processing circuit comprising:
a central processing unit;
a nonvolatile memory unit;
a pulse generating unit; and
a terminal,
wherein said terminal is capable of receiving a first pulse signal, which has a first frequency, from outside of the processing circuit,
wherein said central processing unit is capable of performing a first operation for checking frequency of a generating pulse signal generated by said pulse generating unit,
wherein said nonvolatile memory unit has a plurality of nonvolatile memory cells and receives said generating pulse signal for storing data to ones of said nonvolatile memory cells, and
wherein in performing said first operation by said central processing unit, said central processing unit executes operations for comparing said first frequency of said first pulse signal with said frequency of said generating pulse signal and for adjusting said frequency of said generating pulse signal in accordance with a result of the comparing.
2. The processing circuit according to claim 1 , further comprising a register unit,
wherein said register unit stores a value indicating frequency of said generating pulse signal, and
wherein in performing said first operation, said central processing unit changes said value stored in said register unit for adjusting said frequency of said generating pulse signal.
3. The processing circuit according to claim 2 ,
wherein said central processing unit stores said value stored in said register unit to ones of said nonvolatile memory cells of said nonvolatile memory unit after adjusting said frequency of said generating pulse signal.
4. The processing circuit according to claim 3 , further comprising a random access memory,
wherein program steps of said first operation are stored into said random access memory, and
wherein said central processing unit fetches each of said program steps of said first operation from said random access memory.
5. A testing system having a tester unit coupled with said processing circuit according to claim 4 ,
wherein said tester unit supplies a reference pulse signal having said first frequency as said first pulse signal to said processing circuit via said terminal thereof.
6. The testing system according to claim 5 ,
wherein said tester unit supplies said program steps of said first operation to said processing circuit for storing to said random access memory thereof and for execution by said central processing unit thereof.
7. A testing system having a tester unit coupled with a plurality of processing circuits, each of which comprises:
a central processing unit,
a nonvolatile memory unit,
a pulse generating unit; and
a terminal,
wherein said terminal is capable of receiving a first pulse signal, which has a first frequency, from outside of the processing circuit,
wherein said central processing unit is capable of performing a first operation for checking frequency of a generating pulse signal generated by said pulse generating unit,
wherein said nonvolatile memory unit has a plurality of nonvolatile memory cells and receives said generating pulse signal for storing data to ones of said nonvolatile memory cells,
wherein in performing said first operation by said central processing unit, said central processing unit executes operations for comparing said first frequency of said first pulse signal with said frequency of said generating pulse signal and for adjusting said frequency of said generating pulse signal in accordance with a result of the comparing;
a register unit,
wherein said register unit stores a value indicating frequency of said generating pulse signal,
wherein in performing said first operation, said central processing unit changes said value stored in said register unit for adjusting said frequency of said generating pulse signal,
wherein said central processing unit stores said value stored in said register unit to ones of said nonvolatile memory cells of said nonvolatile memory unit after adjusting said frequency of said generating pulse signal,
a random access memory,
wherein program steps of said first operation are stored into said random access memory,
wherein said central processing unit fetches each of said program steps of said first operation from said random access memory,
wherein said tester unit supplies a reference pulse signal having said first frequency as said first pulse signal to each said processing circuit via said terminal thereof,
wherein said tester unit supplies said program steps of said first operation to each said processing circuit for storing to said random access memory thereof and for execution by said central processing unit thereof, and
wherein said reference pulse signal is supplied to the processing circuits of said plurality in parallel.