Correction of data errors in a memory buffer
View Patent ↗Methods, circuits, and disk drive that correct errors in data that is temporarily stored in a memory buffer are disclosed. An error detection code and an error correction code are generated for data. The data, the error detection code, and the error correction code are stored in the memory buffer. The data is retrieved from the memory buffer and error detected using the error detection code. In response to detecting an error, the error correction code is applied to the retrieved data to generate corrected data.
1. A method of correcting errors in data, comprising:
generating an error correction code for data after the data is retrieved from non-volatile data storage;
buffering the retrieved data, a retrieved error detection code retrieved from non-volatile data storage with the retrieved data, and the generated error correction code in a memory buffer; and
applying the generated error correction code to generate corrected data for detected errors in data read from the memory buffer.
2. The method of claim 1 , wherein the error detection code comprises a cyclic redundancy check (CRC) code based on the data; and wherein generating an error correction code for data retrieved from non-volatile data storage comprises generating a 1-Bit error correction code based on the retrieved data.
3. The method of claim 2 , wherein:
the data read from the memory buffer is error detected using the CRC code; and
in response to detecting an error, the 1-Bit error correction code is applied to correct a single Bit error in the read data so as to generate the corrected data.
4. The method of claim 3 , wherein:
the error detection code comprises a CRC bit pattern;
the error correction code comprises a Hamming code bit pattern; and
buffering the retrieved data, the retrieved error detection code, and the generated error correction code in the memory buffer comprises storing a representation of the retrieved data, the retrieved CRC bit pattern, and the generated Hamming code bit pattern in the memory buffer.
5. The method of claim 1 further comprising:
generating an error detection code and an error correction code with a data storage device for data received from a host device;
temporarily storing the data, the error detection code, and the error correction code in a memory buffer awaiting more permanent storage of the data in the non-volatile data storage media within the data storage device;
detecting errors in data retrieved from the memory buffer using an error detection code retrieved from the memory buffer; and
in response to identifying an error, applying error correction code retrieved from the memory buffer to the retrieved data to generate corrected data that is stored in the non-volatile data storage media.
6. The method of claim 5 , wherein the data storage device comprises a magnetic disk drive, and, in response to detecting an error, error correction code retrieved from the memory buffer is applied to the data retrieved from the memory buffer to generate the corrected data that is written to a magnetic data storage disk in the magnetic disk drive.
7. The method of claim 5 , wherein the data storage device comprises an optical disk drive, and, in response to detecting an error, error correction code retrieved from the memory buffer is applied to the data retrieved from the memory buffer to generate the corrected data that is written to an optical data storage disk in the optical disk drive.
8. The method of claim 5 , wherein, in response to determining that the non-volatile data storage media is ready to receive data from the memory buffer, the data is retrieved from the memory buffer and error detected using error detection code retrieved from the memory buffer.
9. The method of claim 5 , wherein the error detection code is stored with the modified data at a shared logical block address of the non-volatile data storage media.
10. The method of claim 9 , further comprising:
outputting the corrected data to the host device.
11. The method of claim 1 , wherein, in response to a ready signal from a host device, the data is retrieved from the memory buffer and error detected using the error detection code from the memory buffer.
12. A circuit comprising:
a memory buffer; and
at least one controller that generates an error detection code and an error correction code for data; that stores the data, the error detection code, and the error correction code in the memory buffer; that error detects data retrieved from the memory buffer using the error detection code; that, in response to detecting an error, applies the error correction code to the retrieved data to generate corrected data; and that uses the error detection code to determine if the corrected data contains errors.
13. The circuit of claim 12 , wherein the controller generates a cyclic redundancy check (CRC) code based on the data, and generates a 1-Bit error correction code based on the data.
14. The circuit of claim 13 , wherein the controller error detects data retrieved from the memory buffer using the CRC code, and, in response to detecting an error, applies a 1-Bit error correction code to correct a single Bit error in the retrieved data so as to generate the corrected data.
15. The circuit of claim 14 , wherein the controller error generates the CRC code by combining a CRC bit pattern with the data, generates the 1-Bit error correction code by combining a Hamming code bit pattern with the data, and stores a representation of the data, the CRC bit pattern, and the Hamming code bit pattern in the memory buffer.
16. The circuit of claim 12 , wherein the controller generates a new error correction code for data retrieved from a data storage media, temporarily stores the data and error detection code retrieved from the data storage media and the new error correction code in the memory buffer awaiting output of the data to a host device, error detects data retrieved from the memory buffer using the buffered error detection code from the data storage media, that, in response to detecting an error, applies the error correction code to the retrieved data to correct the data for output to the host device.
17. The circuit of claim 12 , wherein the controller comprises:
a cyclic redundancy check (CRC) circuit that error detects data retrieved from the memory buffer using a CRC code; and
a Hamming code processor that, in response to the CRC circuit detecting an error, carries out a Hamming code on the retrieved data to generate corrected data.
18. The circuit of claim 17 , wherein the Hamming code processor comprises a general purpose processor that executes a Hamming code program, and the CRC circuit responds to detection of an error by interrupting the Hamming code processor to initiate execution of the Hamming code program.
19. A disk drive comprising:
a non-volatile data storage disk;
an integrated circuit memory buffer; and
at least one controller that generates an error detection code and an error correction code for data from a host device, that stores the data, the error detection code, and the error correction code in the memory buffer, that error detects data retrieved from the memory buffer using the error detection code, that, in response to detecting an error, applies the error correction code to the retrieved data to generate corrected data, and that writes the corrected data in the disk.