Hardware implementation of loop initialization protocol

1 . A device comprising a loop port controlled by a loop initialization procedure in response to control flags.

2 . The device of claim 1 , wherein the loop port comprises a fibre channel loop port.

3 . The device of claim 1 , further comprising a programmable controller, wherein the loop port comprises a port control circuit that controls the loop initialization procedure in response to the control flags, and wherein the control flags are set by the programmable controller.

4 . The device of claim 3 , wherein the control flags include control bits that indicate whether or not the loop port will participate in one or more loop initialization steps, and the port control circuit controls the loop initialization procedure in response to the control bits.

5 . The device of claim 3 , wherein the control flags include control bits that indicate whether the port control circuit will restart upon occurrence of a timeout, receipt of a bad initialization frame, or upon the receipt of a CLS primitive, and the port control circuit controls the loop initialization procedure in response to the control bits.

6 . The device of claim 3 , wherein the control flags include a control bit that indicates whether the port will act as a Loop Initialization Master, and control bits that indicate whether originating and/or processing of an initialization frame should be performed by the port control circuit or by the programmable controller, and the port control circuit controls the loop initialization procedure in response to the control bit(s).

7 . The device of claim 3 , wherein the control flags include control bits that specify an initialization timeout value, control bits that indicate what the port control circuit should do with improperly formed initialization frames, control bits that specify buffer credit support, and/or control bits that specify whether or not the port supports Fairness in Arbitration, and the port control circuit controls the loop initialization procedure in response to the control bits.

8 . The device of claim 3 , wherein the port control circuit transfers control of the initialization procedure to the programmable controller upon occurrence of a specified event during the initialization procedure.

9 . The device of claim 8 , wherein the port control circuit interrupts the programmable controller upon occurrence of the specified event, wherein the port control circuit provides an indication to the programmable controller of the reason for the interrupt.

10 . The device of claim 3 , further comprising a timer that generates a timer signal in response to a timeout value, wherein the port control circuit delays an initialization event until receipt of the timer signal.

11 . The device of claim 10 , wherein the delayed initialization event comprises sending a LIFA, LIPA, LIHA, LISA, LIRP or LILP initialization frame and/or sending an ARB primitive and/or a CLS primitive.

12 . The device of claim 3 , further comprising a receive buffer and a transmit buffer, wherein the port control circuit decodes received initialization frames and loads the received initialization frames into the transmit buffer.

13 . The device of claim 12 , wherein the port control circuit modifies a received initialization frame of a first frame type to create an initialization frame of a second type.

14 . A method comprising:

initializing a loop initialization protocol (LIP) hardware state machine;

controlling LIP operations with the LIP hardware state machine;

determining if control of the loop initialization operations should be transferred to a programmable controller in response to a predetermined loop initialization event; and

if so, transferring control of the loop initialization operations to the programmable controller.

15 . The method of claim 14 , wherein transferring control of the loop initialization operations to the programmable controller comprises interrupting the programmable controller to request that the programmable controller process the predetermined loop initialization event.

16 . The method of claim 14 , wherein initializing a control register with a flag bit indicative of a protocol for handling the predetermined initialization event, and wherein determining if control of the loop initialization operations should be transferred to a programmable controller in response to the predetermined loop initialization event comprises testing the flag bit in response to occurrence of the predetermined loop initialization event.

17 . The method of claim 16 , wherein the flag bit indicates whether or not the hardware state machine should originate a LISM frame and/or a LIRP frame without firmware intervention.

18 . The method of claim 16 , wherein the flag bit indicates whether or not the hardware state machine should process a LIFA, LIHA, LILP, LIPA LIRP and/or a LISA frame without firmware intervention.

19 . The method of claim 18 , further comprising delaying at least one LIP operation for a predetermined delay period.

20 . The method of claim 19 , wherein delaying a LIP operation comprises delaying sending of a LIP initialization frame for the predetermined delay period.

21 . A method comprising:

initializing a loop initialization protocol (LIP) hardware state machine comprising a plurality of states; and

controlling LIP operations with the LIP hardware state machine;

wherein at least one of the states of the LIP hardware state machine can implement LIP operations in both a loop initialization master mode and a non-master mode.

22 . The method of claim 21 , further comprising:

determining if control of the loop initialization operations should be transferred to a programmable controller in response to a predetermined loop initialization event; and

if so, transferring control of the loop initialization operations to the programmable controller.