Semiconductor interconnection line and method of forming the same
View Patent ↗An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.
1. An interconnection line of a semiconductor device, comprising:
a semiconductor substrate;
a first copper interconnection line formed on the substrate;
an insulating layer pattern formed on the substrate to expose a portion of the first copper interconnection line;
a metal pad layer formed on the exposed portion of the first copper interconnection line;
an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer; and
a second copper interconnection formed in the via hole and the trench and electrically connected to the first copper interconnection line through the metal pad layer.
2. The interconnection line of the semiconductor device of claim 1 , wherein the insulating layer pattern is formed of one selected from a silicon oxide (SiO 2 ) layer, an FSG (Fluoro-Silicate Glass) layer and an insulating layer of a low dielectric constant (low-k) of below 3.0.
3. The interconnection line of the semiconductor device of claim 2 , wherein the intermediate insulating layer is formed of one selected from a silicon oxide (SiO 2 ) layer, an FSG (Fluoro-Silicate Glass) layer, and an insulating layer of a low dielectric constant (low-k) of below 3.0.
4. The interconnection line of the semiconductor device of claim 1 , wherein the metal pad layer is formed of one selected from a W layer, a Ti layer, a TiN layer, a Ta layer and a TaN layer.
5. The interconnection line of the semiconductor device of claim 1 , wherein a portion of the insulating layer pattern is formed on the first copper interconnection line.
6. The interconnection line of the semiconductor device of claim 1 , wherein a portion of the metal pad layer is formed on the insulating layer pattern.
7. The interconnection line of the semiconductor device of claim 1 , wherein the intermediate insulating layer pattern has a portion formed on the insulating layer pattern and a portion formed on the metal pad layer.
8. The interconnection line of the semiconductor device of claim 1 , wherein the second copper interconnection line comprises an electroplated copper layer.
9. The interconnection line of the semiconductor device of claim 1 , wherein the second copper interconnection line comprises an electroless plated copper layer.