Semiconductor memory device with bit line of small resistance and manufacturing method thereof
View Patent ↗A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.
1. A manufacturing method of a semiconductor memory device, comprising steps of:
(a) forming plural linear word lines having a gate insulating film in its lower surface, a first insulating film in its upper surface and a second insulating film in its side surface on a semiconductor substrate;
(b) forming an interlayer insulating film on said word lines;
(c) forming a linear trench running at right angles to said word lines in said interlayer insulating film and exposing said semiconductor substrate between said word lines in said trench;
(d) forming a diffusion bit line in said semiconductor substrate by performing an ion implantation in said trench; and
(e) forming a linear metal bit line in said trench by filling up said trench with a predetermined metal.
2. The semiconductor memory device according to claim 1 , wherein said gate insulating film is an ONO film.
3. The semiconductor memory device according to claim 1 , wherein
said ion implantation is performed from an oblique direction toward said semiconductor substrate inclined along a line of said trench.
4. The semiconductor memory device according to claim 1 , wherein
said ion implantation is performed from a direction perpendicular to said semiconductor substrate.