Method of manufacturing semiconductor device using alignment mark and mark hole
View Patent ↗An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In the present inventions, an insulating film is placed beneath the alignment mark in structure; an alignment mark consisting of said multi-layered film comprising an alignment mark layer and the insulating film, which constitutes a stepped part with an increased difference in level, is first formed, inside a mark hole, in a manner of self-alignment; and then the metal film which is the very cause of the above problem is formed thereon. Since the metal film itself has a stepped shape corresponding to the alignment mark, alignment can be made with great accuracy.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first metal interconnection layer and an insulating film in succession on a semiconductor substrate;
forming a rectangular pattern to be used as an alignment mark on said insulating film;
forming an interlayer insulating film over the entire surface;
forming a mark hole in said interlayer insulating film to expose top and side surfaces of said rectangular pattern;
after the forming the mark hole, removing said insulating film by using the rectangular pattern as a mask to expose a surface of said first metal interconnection layer;
forming a second metal interconnection layer over the entire surface; and
forming an etching mask pattern on said second metal interconnection layer by using said rectangular pattern and said insulating film formed thereunder as the alignment mark.
2. The method of manufacturing a semiconductor device according to claim 1 , further comprising:
planarizing said interlayer insulating film to produce a planarized interlayer insulating film before forming the mark hole in the interlayer insulating film, the mark hole being formed in the planarized interlayer insulating film.
3. The method of manufacturing a semiconductor device according to claim 1 , wherein said etching mask pattern comprises a photoresist pattern.