IP Library Granted Patent US 7,331,737
Granted Patent B2
US 7,331,737 · App. 11/802,363 · Granted Feb 19, 2008

Method of forming a semiconductor device having bonding pad of the second chip thinner than bonding pad of the first chip

Assignee: NEC Electronics Corporation
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Quick Facts
Patent No.
US 7,331,737
App. No.
11/802,363
Granted
Feb 19, 2008
Kind
B2
Abstract

To provide a semiconductor device that enables high integration degree, and a manufacturing method therefor. A multi-chip module according to an embodiment of the present invention includes: a first semiconductor chip having a first bonding pad; a second semiconductor chip having a second bonding pad thinner than the first bonding pad; and a bonding wire connected with each of the first bonding pad and the second bonding pad, the first bonding pad being connected with a first bond side end portion of the bonding wire and the second bonding pad being connected with a second bond side end portion of the bonding wire.

Claims (17)

1. A method of manufacturing a semiconductor device including a plurality of semiconductor chips, comprising:

arranging a first semiconductor chip having a first bonding pad;

arranging a second semiconductor chip having a second bonding pad thinner than the first bonding pad; and

bonding one end of the bonding wire to the first bonding pad and then bonding the other end of the bonding wire to the second bonding pad.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein each of the first bonding pad and the second bonding pad is bonded to the bonding wire through wedge bonding.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein the bonding wire is metal containing Al.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein the first semiconductor chip is an output chip, and the second semiconductor chip is a control circuit chip.

5. The method of manufacturing a semiconductor device according to claim 4 , wherein the first semiconductor chip has a power MOS transistor.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein an external force applied to the second bonding pad upon bonding the second bonding pad to the bonding wire is smaller than an external force applied to the first bonding pad upon bonding the first bonding pad to the bonding wire.

7. The method of manufacturing a semiconductor device according to claim 1 , further comprising:

preparing a lead frame;

mounting the first semiconductor chip on the lead frame;

mounting the second semiconductor chip on the lead frame.

8. The method of manufacturing a semiconductor device according to claim 1 , further comprising:

preparing a lead frame;

mounting the first semiconductor chip on the lead frame;

mounting the second semiconductor chip on the first semiconductor chip.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0456 →
Priority Claims (1)
JP 2005-079520 · Mar 18, 2005 · national
Continuity (2)
Division 1135088900 · Feb 10, 2006
Related Publication 20070224805A1 · Sep 27, 2007