Semiconductor memory device and semiconductor device group
View Patent ↗A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
1. A semiconductor device group comprising a first semiconductor device in which a non-volatile memory device, a logic device and a static random access memory device are integrated on one area of a substrate having a first device isolation region STI structure, and a second semiconductor device in which a logic device and a static random access memory device are integrated on another substrate having a second device isolation region STI structure identical to the first device isolation region STI structure,
wherein a first transfer transistor constituting said static random access memory device of said first semiconductor device has a channel width larger than a channel width of a second transfer transistor forming said static random access memory of said second semiconductor device, and
wherein said first and second transfer transistors have a bit line arranged with predetermined pitch in respective channel width directions.
2. The semiconductor device group as claimed in claim 1 , wherein transistors constituting said static random access memory in said first semiconductor device and a transistor constituting said static random access memory device in said second semiconductor device have an identical channel width in respective channel directions except for said first and second transfer transistors.
3. The semiconductor device group as claimed in claim 1 , wherein said static random access memory of said first semiconductor device and said static random access memory of said second semiconductor device have an identical array of contact plugs.
4. The semiconductor device group as claimed in claim 1 , wherein said first transfer transistor has a device region defined by a linear edge at one side, said device region comprising a first part having a first width corresponding to said larger channel width and a second part having a second width smaller than said first width.
5. The semiconductor device group as claimed in claim 1 , wherein a driver transistor in said first semiconductor device is formed in a U-shaped part with an expansion at one side in a device region by a linear edge at another side.
6. The semiconductor device group as claimed in claim 1 , wherein said first semiconductor device comprises:
a first CMOS inverter including a first n-channel MOS transistor and a first p-channel MOS transistor connected in series at a first node;
a second CMOS inverter including a second n-channel MOS transistor and a second p-channel MOS transistor connected in series at a second node, said second CMOS inverter forming a flip-flop circuit together with said first CMOS inverter;
a first transfer transistor provided between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line; and
a second transfer transistor provided between a second bit line and said second node, said second transfer transistor having a second gate electrode connected to said word line,
said first transfer transistor and said second transfer transistor being formed respectively in first and second device regions defined on said substrate of said first semiconductor device by said device isolation region of STI structure so as to extend in parallel with each other,
a non-volatile memory device being formed on said substrate of said first semiconductor device,
each of said first and second device regions having a rounded corner when viewed in a cross-sectional diagram,
said first transfer transistor contacting with said first bit line at a first bit contact region on said first device region,
said second transfer transistor contacting with said second bit line at a second bit contact region on said second device region,
wherein said first bit contact region is formed in said first device region such that a center of said first bit contact region is offset toward said second device region, and
wherein said second bit contact region is formed in said second device region such that a center of said second bit contact region is offset toward said first device region.