Semiconductor device with a contact plug connected to multiple interconnects formed within
Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9 c which is formed into a beaded shape in a layer underlying two interconnects 11 C and 11 D and which also electrically connects the two interconnects 11 C and 11 D is included. The two interconnects 11 C and 11 D are separated to each other and are formed in a same layer. The contact plug 9 c is simultaneously formed with a contact plug 9 b to be connected to an interconnect 4 b and a contact plug 9 a to be connected to a source/drain region 6.
1. A semiconductor device, comprising:
a first region with Static Random Access Memory (SRAM) cells formed on a substrate thereof;
a power supply hanging portion provided for a predetermined number of said SRAM cells;
a second region between said first region and said power supply hanging portion; and
an embedded interconnect, which electrically connects said first region to said power supply hanging portion, being continuous from said first region to said power supply hanging portion,
said first region, said second region, and said supply power hanging portion being continuous and sequentially disposed in a direction horizontal to said substrate.
2. A semiconductor device, comprising:
a contact plug formed into a beaded shape or a slit shape in a layer underlying two interconnects, said contact plug electrically connecting said two interconnects; and
a metal-insulator-metal (MIM) capacitor element, said MIM capacitor element comprising:
one of said two interconnects;
a dielectric film disposed on said one of said two interconnects; and
an electrode disposed on said dielectric film,
wherein said dielectric film is disposed only on said one of said two interconnects, entirely in an upper layer of said interconnects, and
wherein said electrode is disposed in a different layer than said other one of said two interconnects.
3. The semiconductor device according to claim 1 , wherein said embedded interconnect is disposed entirely below, and is in direct contact with, said first region, said second region, and said power supply hanging portion.
4. The semiconductor device according to claim 1 , wherein said first region comprises a metal-insulator-metal (MIM) capacitor element, said MIM capacitor element comprising:
an interconnect;
a dielectric film disposed on said interconnect; and
an electrode disposed on said dielectric film, said electrode comprising a metal barrier layer and a metal layer, said metal layer being disposed on a surface of said metal barrier layer.
5. The semiconductor device according to claim 4 , wherein ends of said dielectric film and said electrode extend up to a vicinity of a middle section of said second region.