Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device in accordance with the present invention is provided with a plurality of memory cells of field effect transistor type, a source bias control circuit, and a drain bias control circuit. The source bias control circuit variably sets the potential of a source line connected in common to the sources of the plurality of memory cells at the time of write operation. The drain bias control circuit variably sets the potential of the drains of the plurality of memory cells at the time of write operation according to the potential of the source line.
1. A semiconductor memory device comprising:
a memory cell array including a common line and a plurality of memory cells, all of sources of said memory cells being connected in common to said common line; and
a data write circuit responsive to write mode to perform a data write operation by using a channel hot electron method on said memory cells, said data write circuit being operable to supply a variable potential to one of a drain of said memory cells in response to a potential of said common line in said write mode.
wherein said data write circuit secures a drain-source voltage to prevent a selected cell from being failure in said write mode.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein at least one of said memory cells has an off-leakage current.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein a threshold voltage of said memory cell is at a depletion level.
4. The nonvolatile semiconductor memory device according to claim 1 , wherein at least one of said memory cells comprises an unselected cell.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein said data write circuit includes a drain bias control circuit and a source bias control circuit.
6. The semiconductor memory device according to claim 5 , wherein said drain bias control circuit sets a potential of a drain of said memory cell to a higher level in response to said common line rises.
7. The semiconductor memory device according to claim 5 , wherein said source bias control circuit sets a potential of said common line to a positive level.