Decoding LDPC (low density parity check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph
View Patent ↗Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. Decoding of LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
a check node processing module that is operable to update a first check edge message using a plurality of bit edge messages by calculating a product of terms function wherein those terms correspond to the plurality of bit edge messages thereby generating a second check edge message; and
a bit node processing module that is operable to update a first bit edge message of the plurality of bit edge messages using a plurality of check edge messages, that includes the second check edge message, thereby generating a second bit edge message; and wherein:
the second bit edge message is employed to make a soft estimate of at least one information bit encoded within the LDPC coded signal.
2. The decoder of claim 1 , wherein:
the bit edge message is an initialized bit edge message.
3. The decoder of claim 1 , wherein:
the first bit edge message corresponds to a first edge that couples a first bit node to a first check node within an LDPC bipartite graph that corresponds to an LDPC code by which the LDPC coded signal is generated; and
the first check edge message corresponds to a second edge that couples a second check node to a second bit node within the LDPC bipartite graph that corresponds to the LDPC code by which the LDPC coded signal is generated.
4. The decoder of claim 1 , wherein:
the check node processing module and the bit node processing module are implemented within a single processor that is operable to perform both check node processing and bit node processing.
5. The decoder of claim 1 , wherein:
the check node processing module and the bit node processing module are implemented within a single processor that is operable to perform both check node processing and bit node processing; and
the single processor is operable to generate the first bit edge message which is an initialized bit edge message.
6. The decoder of claim 1 , further comprising:
a hard limiter that is operable to make a hard estimate of the soft estimate of at least one information bit encoded within the LDPC coded signal; and
a syndrome calculator module that is operable to employ the hard estimate to determine whether each syndrome of a plurality of syndromes associated with the LDPC code is equal to zero; and wherein:
when, during a decoding iteration, the syndrome calculator determines that each syndrome of the plurality of syndromes associated with the LDPC code is equal to zero, then the decoding iteration is a final decoding iteration; and
when, during the decoding iteration, the syndrome calculator determines that each syndrome of the plurality of syndromes associated with the LDPC code is not equal to zero, then the decoder is operable to perform at least one additional decoding iteration.
7. The decoder of claim 1 , wherein:
the bit node processing module is operable to perform likelihood processing when updating the first bit edge message; and
the check node processing module is operable to perform likelihood processing when updating the first check edge message.
8. The decoder of claim 1 , wherein:
the decoder is implemented within a communication device; and
the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.
9. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
a check node processing module that is operable to update a first check edge message using a plurality of bit edge messages while operating in a logarithmic domain by calculating a sum of terms function wherein those terms correspond to the plurality of bit edge messages thereby generating a second check edge message; and
a bit node processing module that is operable to update a first bit edge message of the plurality of bit edge messages using a plurality of check edge messages, that includes the second edge message, thereby generating a second bit edge message; and wherein:
the second bit edge message is employed to make a soft estimate of at least one information bit encoded within the LDPC coded signal.
10. The decoder of claim 9 , wherein:
the first bit edge message corresponds to a first edge that couples a first bit node to a first check node within an LDPC bipartite graph that corresponds to an LDPC code by which the LDPC coded signal is generated; and
the first check edge message corresponds to a second edge that couples a second check node to a second bit node within the LDPC bipartite graph that corresponds to the LDPC code by which the LDPC coded signal is generated.
11. The decoder of claim 9 , wherein:
the check node processing module and the bit node processing module are implemented within a single processor that is operable to perform both check node processing and bit node processing.
12. The decoder of claim 9 , wherein:
the check node processing module and the bit node processing module are implemented within a single processor that is operable to perform both check node processing and bit node processing; and
the single processor is operable to generate the first bit edge message which is an initialized bit edge message.
13. The decoder of claim 9 , further comprising:
a hard limiter that is operable to make a hard estimate of the soft estimate of at least one information bit encoded within the LDPC coded signal; and
a syndrome calculator module that is operable to employ the hard estimate to determine whether each syndrome of a plurality of syndromes associated with the LDPC code is equal to zero; and wherein:
when, during a decoding iteration, the syndrome calculator determines that each syndrome of the plurality of syndromes associated with the LDPC code is equal to zero, then the decoding iteration is a final decoding iteration; and
when, during the decoding iteration, the syndrome calculator determines that each syndrome of the plurality of syndromes associated with the LDPC code is not equal to zero, then the decoder is operable to perform at least one additional decoding iteration.
14. The decoder of claim 9 , wherein:
the bit node processing module is operable to perform likelihood processing when updating the first bit edge message; and
the check node processing module is operable to perform likelihood processing when updating the first check edge message.
15. The decoder of claim 9 , wherein:
the decoder is implemented within a communication device; and
the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.
16. A method for decoding an LDPC (Low Density Parity Check) coded signal, the method comprising:
performing check node processing that includes updating a first check edge message using a plurality of bit edge messages by calculating a product of terms function wherein those terms correspond to the plurality of bit edge messages thereby generating a second check edge message; and
performing bit node processing that includes updating a first bit edge message of the plurality of bit edge messages using a plurality of check edge messages, that includes the second check edge message, thereby generating a second bit edge message; and
employing the second bit edge message to make a soft estimate of at least one information bit encoded within the LDPC coded signal.
17. The method of claim 16 , wherein:
the check node processing and the bit node processing are both performed within a single processor.
18. The method of claim 16 , wherein:
the first bit edge message corresponds to a first edge that couples a first bit node to a first check node within an LDPC bipartite graph that corresponds to an LDPC code by which the LDPC coded signal is generated; and
the first check edge message corresponds to a second edge that couples a second check node to a second bit node within the LDPC bipartite graph that corresponds to the LDPC code by which the LDPC coded signal is generated.
19. The method of claim 16 , further comprising:
making a hard estimate of the soft estimate of at least one information bit encoded within the LDPC coded signal;
employing the hard estimate to determine whether each syndrome of a plurality of syndromes associated with the LDPC code is equal to zero;
when, during a decoding iteration, it is determined that each syndrome of the plurality of syndromes associated with the LDPC code is equal to zero, identifying the decoding iteration as a final decoding iteration; and
when, during the decoding iteration, it is determined that each syndrome of the plurality of syndromes associated with the LDPC code is not equal to zero, performing at least one additional decoding iteration.
20. The method of claim 16 , wherein:
the method is performed within a decoder;
the decoder is implemented within a communication device; and
the communication device is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.