Design flow for shrinking circuits having non-shrinkable IP layout

1. A method for processing an integrated circuit, the method comprising:

providing a first integrated circuit representation having a first circuit layout scale, wherein the first integrated circuit representation comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout;

generating a second integrated circuit representation having a second circuit layout scale smaller than the first circuit layout scale, wherein the step of generating the second integrated circuit representation comprises:

shrinking the shrinkable circuit to the second circuit layout scale, wherein the step of shrinking the shrinkable circuit comprises:

generating a first phantom from the shrinkable circuit;

shrinking the first IP layout to generate a third IP layout having the second circuit layout scale; and

merging the third IP layout with a final top layout under the second circuit layout scale;

merging the second IP layout with the shrinkable circuit of the second circuit layout scale to generate a final integrated circuit representation wherein the step of merging the second IP layout comprises:

generating a second phantom from the non-shrinkable circuit;

blowing-up the second phantom to generate a third phantom;

placing and routing the first and the third phantoms to generate a top-level layout;

shrinking the top-level layout to the second circuit layout scale to generate a final top-level layout; and

merging the second IP layout with the final top-level layout; and

implementing the final integrated circuit representation on a chip.

2. The method of claim 1 , wherein the step of blowing-up the second phantom comprises inner-snapping pins in the third phantom to a first grid.

3. The method of claim 2 , wherein the final top-level layout has a second grid smaller than the first grid, and wherein features in the final top-level layout overlap the second grid without snapping.

4. The method of claim 1 , wherein the step of blowing-up the second phantom comprises outer-snapping a boundary of the third phantom to a first grid.

5. The method of claim 1 further comprising a design rule check against the final integrated circuit representation.

6. A method for processing an integrated circuit, the method comprising:

providing a first integrated circuit representation having a first circuit layout scale, wherein the first integrated circuit representation comprises a shrinkable circuit and a non-shrinkable circuit represented by a first and a second intellectual property (IP) layout, respectively;

generating a first phantom from the shrinkable circuit;

generating a second phantom from the non-shrinkable circuit;

blowing-up the second phantom by a first factor to generate a third phantom;

placing and routing the first and the third phantoms to generate a top-level layout;

shrinking the top-level layout by a second factor to generate a final top-level layout, wherein the second factor is substantially inverted from the first factor;

shrinking the first IP layout by the second factor to generate a third IP layout having a second circuit layout scale;

merging the second and the third IP layouts with the final top-level layout to generate a final integrated circuit representation; and

implementing the final integrated circuit representation on a chip.

7. The method of claim 6 , wherein the step of blowing-up the second phantom comprises inner-snapping pins in the third phantom to a first grid.

8. The method of claim 7 , wherein blowing-up the second phantom comprises outer-snapping a boundary of the third phantom to the first grid.

9. The method of claim 7 , wherein the final top-level layout has a second grid smaller than the first grid.

10. The method of claim 6 further comprising a design rule check against the final integrated circuit representation.

11. The method of claim 6 further comprising a layout-verses-schema (LSV) comparison check.

12. A production tool for processing an integrated circuit, wherein the integrated circuit has a first circuit layout scale, and wherein the integrated circuit comprises a shrinkable circuit and a non-shrinkable circuit represented by a first and a second intellectual property (IP) layout, respectively, the production tool comprising:

first computer program codes for generating a first phantom from the shrinkable circuit;

second computer program codes for generating a second phantom from the non-shrinkable circuit;

third computer program codes for blowing-up the second phantom by a first factor to generate a third phantom;

fourth computer program codes for placing and routing the first and the third phantoms to generate a top-level layout;

fifth computer program codes for shrinking the top-level layout by a second factor to generate a final top-level layout;

sixth computer program codes for shrinking the first IP layout to generate a third IP layout having a second circuit layout scale; and

seventh computer program codes for merging the second and the third IP layouts with the final top-level layout to generate a final integrated circuit representation.

13. The production tool of claim 12 , wherein the second factor has a substantially inverted value of the first factor, and wherein the first IP layout is shrink by the second factor.

14. The production tool of claim 12 , wherein the third computer program codes for blowing-up the second phantom further comprise additional program codes for inner-snapping pins in the third phantom to a first grid.

15. The production tool of claim 14 , wherein the third computer program codes for blowing-up the third phantom further comprise program codes for outer-snapping a boundary of the third phantom to the first grid.

16. The production tool of claim 14 , wherein the final top-level layout has a second grid smaller than the first grid.

17. The production tool of claim 12 further comprising computer program codes for checking design rules against the final integrated circuit representation.