IP Library Granted Patent US 7,932,175
Granted Patent B2
US 7,932,175 · App. 11/807,745 · Granted Apr 26, 2011

Method to form a via

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,932,175
App. No.
11/807,745
Granted
Apr 26, 2011
Kind
B2
Abstract

A method for forming a via, comprising (a) providing a structure comprising a mask ( 210 ) disposed on a semiconductor substrate ( 203 ), wherein the structure has an opening ( 215 ) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer ( 219 ) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal ( 221 ) over the first portion of the second conductive layer.

Claims (52)

1. A method for making a semiconductor device, comprising:

providing a structure comprising a mask disposed on a semiconductor substrate, wherein the structure has an opening defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer sandwiched between first and second dielectric layers, and wherein the first electrically conductive layer, the first dielectric layer and the second dielectric layer are coextensive;

depositing a second electrically conductive layer such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening;

removing the second portion of the second conductive layer; and

depositing a first metal over the first portion of the second conductive layer.

2. The method of claim 1 , wherein the second conductive layer comprises a metal seed layer.

3. The method of claim 2 , further comprising forming a barrier layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening, wherein the barrier layer is in electrical contact with the first conductive layer, and wherein the step of removing the second portion of the second conductive layer also removes the second portion of the barrier layer.

4. The method of claim 3 , wherein the seed layer is deposited over the barrier layer.

5. The method of claim 4 , wherein the barrier layer is a metal layer.

6. The method of claim 2 , wherein the seed layer comprises copper, and wherein the first metal comprises copper.

7. The method of claim 1 , wherein the first and second conductive layers are metal layers.

8. The method of claim 1 , wherein the second portion of the second conductive layer is removed from the portion of the mask adjacent to the opening through chemical mechanical polishing (CMP).

9. The method of claim 1 , wherein the mask comprises a first dielectric layer disposed between the first conductive layer and the substrate.

10. The method of claim 9 , wherein the mask further comprises a second dielectric layer, and wherein the layer is disposed between the first and second dielectric layers.

11. The method of claim 10 , wherein the first and second dielectric layers comprise tetraethylorthosilicate (TEOS).

12. The method of claim 1 wherein, prior to deposition of the second conductive layer, a dielectric layer is formed over the surfaces of the opening.

13. The method of claim 12 , wherein the dielectric layer is formed by a plasma nitridation step.

14. The method of claim 1 , wherein the first metal is deposited by electrochemical deposition.

15. The method of claim 1 , wherein the semiconductor substrate is a wafer, and wherein the first conductive layer is disposed between first and second dielectric layers.

16. The method of claim 15 , wherein the first metal is deposited by electrochemical deposition, and wherein at least one of the first and second dielectric layers is removed from the edge of the wafer by etching prior to the electrochemical deposition.

17. The method of claim 1 , wherein the opening is a through semiconductor via (TSV).

18. The method of claim 1 , wherein said first portion and said second portion of said second conductive layer are adjoining.

19. The method of claim 1 wherein, after removing the second portion of the second conductive layer, the second conductive layer extends only over the surfaces of the opening.

20. The method of claim 1 , wherein said second portion of said second conductive layer extends to the edge of said opening.

21. A method for making a semiconductor device, comprising:

providing a semiconductor substrate having a layer stack disposed thereon which comprises a first electrically conductive layer sandwiched between first and second dielectric layers;

patterning the layer stack so as to form a first opening therein which exposes a portion of the substrate;

using the patterned layer stack as a first mask to etch the substrate, thus forming a second opening which includes the first opening and which extends into the substrate;

depositing a second electrically conductive layer such that the second conductive layer is in electrical contact with the first electrically conductive layer, wherein the second electrically conductive layer has a first portion that extends over the surfaces of the second opening and a second portion that extends over a portion of the mask adjacent to the second opening;

removing the second portion of the second conductive layer; and

depositing a first metal over the first portion of the second electrically conductive layer.

22. The method of claim 21 , wherein patterning the layer stack comprises:

depositing a layer of photoresist over the layer stack;

patterning the layer of photoresist so as to form a second mask having an opening therein which exposes a portion of the layer stack; and

using the second mask to pattern the layer stack.

23. The method of claim 21 , wherein using the second mask to pattern the layer stack involves etching the layer stack with a first etch, and wherein using the patterned layer stack as a first mask to etch the substrate involves etching the substrate with a second etch which is distinct from said first etch.

24. The method of claim 22 , wherein the first electrically conductive layer and the first and second dielectric layers are coextensive in the patterned layer stack.

25. The method of claim 21 , wherein the portion of the second opening which extends into the substrate is coextensive with the first opening.

26. The method of claim 22 , wherein the patterned layer of photoresist is removed after the layer stack is patterned but before the patterned layer stack is used as a first mask to etch the substrate.

27. The method of claim 21 , wherein the layer stack is formed by:

depositing a first dielectric material on the substrate, thereby forming the first dielectric layer;

depositing a first conductive material on the first dielectric layer, thereby forming the first electrically conductive layer; and

depositing a second dielectric material on the first electrically conductive layer, thereby forming the second dielectric layer.

28. The method of claim 27 , wherein the first electrically conductive layer is continuous.

29. The method of claim 27 , wherein the first electrically conductive layer is of uniform composition.

30. The method of claim 21 , wherein the second electrically conductive layer is in physical contact with the first electrically conductive layer, the first dielectric layer and the second dielectric layer.

31. The method of claim 21 , wherein the second electrically conductive layer is in physical contact with the edges of the first electrically conductive layer, the first dielectric layer and the second dielectric layer which are exposed by the first opening.

32. The method of claim 21 , wherein the second electrically conductive layer comprises a metal seed layer.

33. The method of claim 32 , further comprising forming a barrier layer having a first portion which extends over the surfaces of the second opening and a second portion which extends over a portion of the mask adjacent to the second opening, wherein the barrier layer is in electrical contact with the first electrically conductive layer, and wherein removing the second portion of the second conductive layer includes removing the second portion of the barrier layer.

34. The method of claim 21 , wherein removing the second portion of the second conductive layer exposes the second dielectric layer.

35. The method of claim 21 , wherein the first metal is deposited over the first portion of the second conductive layer after the second portion of the second conductive layer is removed but before the second dielectric layer is removed.

36. The method of claim 35 , wherein the second dielectric layer is removed after the first metal is deposited over the first portion of the second conductive layer.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0655 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Nov 1, 2007
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 020045/0448 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2007
From: CHATTERJEE, RITWIK; ACOSTA, EDDIE; GARCIA, SAM S.; MATHEW, VARUGHESE
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 019418/0728 →