Doped plug for CCD gaps
A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.
1. A method of providing a Charged Coupled Device (CCD) comprising:
providing at least two gates configured to hold and/or transfer charge;
situating a plugged gap between two gate structures, the plugged gap further comprising a dopant material;
wherein situating a plugged gap further comprises situating two plug gaps, each gap being situated between two gates, and
splitting a transfer charge between the two plugged gaps.
2. The method of claim 1 further comprising preventing random affects of surface charges.
3. The method of claim 1 further comprising equally matching the two plugged gaps and splitting the transfer charge according to a ratio determined by gate and active-area geometries.
4. The method of claim 3 further comprising equally splitting the transfer charge.
5. The method of claim 1 further comprising doping the plugged gap with a self aligned implantation.
6. The method of claim 1 wherein the dopant material is a p-type or n-type dopant.
7. The method of claim 1 further comprising providing a conductive region spanning the entire gap, thereby causing a uniform affect of surface charges along an entire gap region.
8. A method of providing a Charged Coupled Device (CCD) comprising:
providing at least two gates configured to hold and/or transfer a transferring charge;
equally matching at least two plugged gaps via a matched dopant material;
situating the at least two plugged gaps between two gate structures; and
equally splitting a charge among the at least two plugged gaps.