Nitride-based semiconductor light emitting device and method of manufacturing the same

1. A method of manufacturing a nitride-based semiconductor light emitting device, comprising:

forming a sacrificial layer on a substrate;

forming a passivation layer on the sacrificial layer;

forming a plurality of masking dots of a metal nitride on the passivation layer;

laterally epitaxially growing a nitride-based semiconductor layer on the passivation layer using the masking dots as masks;

forming a semiconductor device on the nitride-based semiconductor layer; and

wet etching the sacrificial layer to separate or remove the substrate from the semiconductor device.

2. The method of claim 1 , wherein the passivation layer protects the sacrificial layer in a reaction gas atmosphere for growing a crystal and epitaxially grows a semiconductor layer.

3. The method of claim 1 , wherein the semiconductor device includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer.

4. The method of claim 3 , further comprising:

forming an n-electrode and a p-electrode on a lower surface of the passivation layer and an upper surface of the p-type semiconductor layer, respectively.

5. The method of claim 1 , wherein the metal nitride is one selected from the group consisting of Ti, Ni, Co, Pd, Cr, Rd, Pt, and Au.

6. The method of claim 1 , wherein a diameter of each of the masking dots is within a range between about 30 nm and about 2000 nm.

7. The method of claim 1 , wherein a ratio of an occupied area of the masking dots on an area of an upper surface of the passivation layer is within a range between about 20% and about 80%.

8. The method of claim 1 , wherein the sacrificial layer is formed of one selected from the group consisting of SiO 2 , GeO 2 , SnO, ZnO, MgO, BeO, CaO, CdO, MnO, NiO, CuO, Cu 2 O, AgO, Ag 2 O, WO 3 , Cr 2 O 3 , CrO 3 , Al 2 O 3 , In 2 O 3 , B 2 O 3 , Ga 2 O 3 , Ti 2 O 3 , CoO, ITO (Indium Tin Oxide), IZO (In x Zn (1−x) O), AZO (Al-doped ZnO), and ZnMgO.

9. The method of claim 1 , wherein the sacrificial layer is formed of one selected from the group consisting of SiN, SiON, and ZnS.

10. The method of claim 1 , wherein the sacrificial layer is formed using a vapor deposition method including one of a CVD (chemical vapor deposition) method and a PVD (physical vapor deposition) method.

11. The method of claim 1 , wherein the sacrificial layer is formed to a thickness between about 0.01 μm and about 20 μm.

12. The method of claim 1 , wherein the passivation layer is formed of one selected from the group consisting of SiC, GaAs, AlAs, InAs, AlGaAs, a Group-III nitride, and a Group-IV nitride.

13. The method of claim 12 , wherein the Group-III nitride includes at least one selected from the group consisting of GaN, AlN, InN, BN, InGaN, and AlGaN.

14. The method of claim 12 , wherein the Group-IV nitride includes at least one selected from the group consisting of SiN, CN, and SiCN.

15. The method of claim 1 , wherein the passivation layer is formed using a PVD method.

16. The method of claim 15 , wherein the PVD method includes one of a sputtering method, a MBE (molecular beam epitaxy) method, and an evaporation method.

17. The method of claim 1 , wherein the passivation layer is formed to a thickness between about 0.01 μm and about 20 μm.

18. The method of claim 1 , wherein the wet etching uses an acid or alkali-based etchant for selectively etching the sacrificial layer.

19. The method of claim 18 , wherein the acid-based etchant includes one of fluoric acid, hydrochloric acid, sulfuric acid, nitric acid, and phosphoric acid solutions.

20. The method of claim 1 , further comprising:

thermally treating the sacrificial layer in a gas atmosphere including at least one selected from the group consisting of nitrogen, oxygen, and argon or in a vacuum atmosphere between the formation of the sacrificial layer and the formation of the passivation layer.

21. The method of claim 20 , wherein the sacrificial layer is thermally treated at a temperature between about 100° C. and about 1400° C. for a time between about 0.1 minutes and about 180 minutes.

22. The method of claim 21 , wherein the temperature for the thermal treatment is achieved by increasing a temperature of an interior of a reaction chamber with the substrate in a ratio between about 1° C. and about 100° C. per second.

23. The method of claim 1 , further comprising:

thermally treating the passivation layer in a gas atmosphere comprising at least one selected from the group consisting of nitrogen, oxygen, and argon or in a vacuum atmosphere between the formation of the passivation layer and the formation of the masking dots.

24. The method of claim 23 , wherein the passivation layer is thermally treated at a temperature between about 100° C. and about 1400° C. for a time between about 0.1 minutes and about 180 minutes.

25. The method of claim 24 , wherein the temperature for the thermal treatment of the passivation layer is achieved by increasing the temperature of the interior of the reaction chamber with the substrate in a ratio between about 1° C. and about 100° C. per second.

26. The method of claim 1 , wherein forming the plurality of masking dots of the metal nitride comprises:

forming at least one metal layer on the passivation layer;

thermally treating the metal layer in a H 2 atmosphere to form a plurality of metal dots on the passivation layer; and

thermally treating the plurality of metal dots in a NH 3 atmosphere to form the plurality of masking dots.

27. The method of claim 26 , wherein the metal layer is formed of one selected from the group consisting of Ti, Ni, Co, Pd, Cr, Rd, Pt, and Au.

28. The method of claim 27 , wherein if the metal layer is formed of a plurality of layers, the plurality of layers are formed of different metals.

29. The method of claim 26 , wherein the metal layer is formed to a thickness between about 5 nm and about 100 nm.

30. The method of claim 26 , wherein the metal layer includes a Ni layer having a thickness between about 2 nm and about 10 nm and a Ti layer having a thickness between about 3 nm and about 98 nm, which are sequentially stacked on the passivation layer.

31. The method of claim 26 , wherein the metal layer is formed using a PVD method.

32. The method of claim 26 , wherein the metal layer is thermally treated at a temperature between about 400° C. and about 1000° C. for a time between about 0.5 minutes and about 10 minutes.

33. The method of claim 32 , wherein the temperature for the thermal treatment of the metal layer is achieved by increasing the temperature of the interior of the reaction chamber with the substrate in a ratio between about 1° C. and about 100° C. per second.

34. The method of claim 26 , wherein the metal dots are thermally treated at a temperature between about 1000° C. and about 1400° C. for a time between about 0.5 minutes and about 10 minutes.

35. The method of claim 34 , wherein the temperature for the thermal treatment of the metal dots is achieved by increasing the temperature of the interior of the reaction chamber with the substrate in a ratio between about 1° C. and about 100° C. per second.

36. The method of claim 1 , wherein the nitride-based semiconductor layer is formed of Al x Ga (1−X) N (about 0≦X<about 1).

37. The method of claim 1 , wherein the nitride-based semiconductor layer is formed to a thickness between about 0.01 μm and about 20 μm.

38. The method of claim 1 , wherein the nitride-based semiconductor layer is formed using a MOCVD (metal organic chemical vapor deposition) method.

39. The method of claim 1 , wherein n-type dopant is further doped on the nitride-based semiconductor layer.

40. The method of claim 1 , wherein the semiconductor device is formed using a MOCVD method.

41. The method of claim 1 , wherein the substrate is a nonconductive substrate.

42. The method of claim 41 , wherein the nonconductive substrate is a sapphire substrate.

43. A nitride-based semiconductor light emitting device comprising:

a passivation layer;

a plurality of masking dots of a metal nitride on the passivation layer;

a nitride-based semiconductor layer on the passivation layer;

a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the nitride-based semiconductor layer; and

an n-electrode and a p-electrode on a lower surface of the passivation layer and an upper surface of the p-type semiconductor layer, respectively.