Semiconductor device and operation control method of semiconductor device
A semiconductor device according to an embodiment of the present invention includes: a first semiconductor chip performing a predetermined operation based on a first control signal or a second control signal; a second semiconductor chip selectively outputting the external first control signal or the internal second control signal; and a line inputting the first or second control signal output from the second semiconductor chip to the first semiconductor chip.
1 . A semiconductor device, comprising:
a first semiconductor chip performing a predetermined operation based on a first control signal or a second control signal;
a second semiconductor chip selectively outputting the external first control signal or the internal second control signal; and
a line inputting the first or second control signal output from the second semiconductor chip to the first semiconductor chip.
2 . The semiconductor device according to claim 1 , wherein the second semiconductor chip outputs the first control signal to a predetermined terminal if the first control signal is externally supplied, and outputs the internal second control signal to the predetermined terminal if the first control signal is not externally supplied.
3 . The semiconductor device according to claim 1 , wherein the second semiconductor chip includes:
a selector selecting a path for outputting the first control signal or a path for outputting the second control signal; and
a control register determining a path selected by the selector.
4 . A semiconductor chip comprising:
selector outputting a first control signal to a predetermined terminal if the first control signal is externally supplied, and outputting an internal second control signal to the predetermined terminal if the first control signal is not externally supplied.
5 . The semiconductor chip according to claim 4 , wherein a selector selecting a path for outputting the first control signal or a path for outputting the second control signal is provided.
6 . The semiconductor chip according to claim 4 , wherein a control register determining a path selected by the selector is provided.
7 . An operation control method of a semiconductor device including a first semiconductor chip and a second semiconductor chip, comprising:
outputting a first control signal to a predetermined terminal with the second semiconductor chip if the first control signal is externally supplied;
outputting a second control signal generated in the second semiconductor chip to the predetermined terminal with the second semiconductor chip if the first control signal is not externally supplied; and
inputting the first or second control signal output to the predetermined terminal to the first semiconductor chip.
8 . A semiconductor device, comprising:
a first external terminal;
a first semiconductor chip including a first terminal electrically connected with the first external terminal and a second terminal selecting a first control signal input to the first terminal or an internal second control signal to output the selected signal; and
a second semiconductor chip including a third terminal electrically connected with the second terminal, and controlled in response to the first control signal and the second control signal.
9 . The semiconductor device according to claim 8 , wherein the first semiconductor chip includes a selector circuit selecting one of the first and second control signals to output the selected signal to the second terminal.
10 . The semiconductor device according to claim 9 , wherein the selector circuit includes a register determining whether to select the first control signal or the second control signal.
11 . The semiconductor device according to claim 10 , further comprising:
a second external terminal,
wherein a signal input from the second external terminal is written to the register.
12 . The semiconductor device according to claim 8 , wherein the second terminal and the third terminal cannot be directly accessed from the outside.
13 . The semiconductor device according to claim 8 , wherein the second terminal, the third terminal, and a line connecting the second and third terminals are sealed.
14 . The semiconductor device according to claim 8 , wherein the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.
15 . The semiconductor device according to claim 8 , wherein the third terminal is a terminal to input a chip select signal.