Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects
View Patent ↗Wire bond pad and solder ball or controlled collapse chip connections C4 are combined on a planar surface of a an integrated circuit device to provide a die. Known good die (KGD) testing is optionally performed using wire bond connections or stress tolerant solder ball connections. The KGD testing is conducted after the integrated circuit dies are diced from a wafer. Solder ball or C4 array connections which withstand thermal stress are used to KGD test the die prior to final use of the wire bond pad connections to an end use device. Alternatively, wire bond pads are used to test the die while maintaining the solder ball or C4 array in a pristine condition for bonding to a final end product device. Both testing with the solder ball C4 array contacts and with the wire bond connections provides metallurgical connections for the KGD test. The solder ball or C4 array is connected to the wire bond pads and either connection can be used to burn-in test the die.
1. An end use device having a known good die (KGD), the KGD having solder ball array and wire bond connections;
the KGD having solder ball array connections on a planar KGD surface;
the KGD having an array of wire bond connections on the planar KGD surface;
the KGD having electrical connections between all of the solder ball array connections and the wire bond connections;
wherein the KGD is a KGD which is thermal stress tolerance tested prior to mounting the KGD on the end use device by a test device connected to the KGD by the wire bond connections or in the alternative by the solder ball connections;
wherein when either the wire bond connections are used or the solder ball connections are used for a known good die test, the other connections are connected to the end use device; and the connections used for the known good die test are not connected to the end use device or any other device, when the KGD is connected to the end use device.
2. The end use device in accordance with claim 1 , wherein when either the wire bond connections or solder ball connections is used for the known good die test, the other is not affected by the known good die (KGD) test and remains pristine until connected to the end use device.
3. The end use device in accordance with claim 1 , wherein the solder ball array connections or wire bond connections which are used when the die is tested are not removed from the die.
4. The end use device in accordance with claim 1 , wherein connections to the test device are metallurgical connections.
5. The end use device in accordance with claim 1 , wherein the solder ball array connections are controlled collapse chip connections.
6. An integrated circuit (IC) die, comprising:
a plurality of solder balls on a planar surface of the IC die;
a plurality of wire bond pads on the planar surface; and
one or more conductor paths interconnecting one or more of the plurality of solder balls with one or more of the plurality of wire bond pads, wherein the one or more conductor paths interconnect the one or more solder balls and the one or more wire bond pads such that either the plurality of solder balls or the plurality of wire bond pads are configured to be used to test the IC die, and wherein the plurality of solder balls or the plurality of wire bond pads not configured to be used to test the IC die are configured to be used to connect the IC die to an end-use device;
wherein the IC die is a known good die, wherein the plurality of wire bond pads are configured to be used to connect the IC die to the end-use device and are pristine, and wherein the plurality of solder balls are configured to be used to test the IC die, are non-pristine, are unusable for connecting to the end-use device, and include one or more distorted solder balls.
7. The IC die of claim 6, wherein the distorted solder balls include one or more solder balls having a taffy-pull configuration.
8. A multi-chip module, comprising:
a substrate including a plurality of integrated circuit (IC) dies;
a plurality of solder balls on a surface of the substrate and directly contacting one or more of the plurality of IC dies;
a plurality of wire bond pads on the surface of the substrate; and
one or more conductor paths interconnecting one or more of the plurality of solder balls with one or more of the plurality of wire bond pads, wherein the one or more conductor paths interconnect the one or more solder balls and the one or more wire bond pads such that either the plurality of solder balls or the plurality of wire bond pads are configured to be used to test the one or more of the plurality of IC dies, and wherein the plurality of solder balls or the plurality of wire bond pads not configured to be used to test the one or more of the plurality of IC dies are configured to be used to connect the one or more of the plurality of IC dies to an end-use device;
wherein the IC dies are known good dies, wherein the plurality of wire bond pads are configured to be used to connect the one or more of the plurality of IC dies to an end-use device and are pristine, wherein the plurality of solder balls are configured to be used to test the one or more of the plurality of IC dies, are non-pristine, are unusable for connecting to the end-use device, and include one or more distorted solder balls, and wherein the distorted solder balls include one or more solder balls having a taffy-pull configuration.
9. The multi-chip module of claim 8, wherein at least one of the plurality of IC dies comprise a micro-electro-mechanical system (MEMS) IC die.
10. An apparatus, comprising:
a micro-electro-mechanical system (MEMS) end-use device; and
an integrated circuit (IC) die coupled to the MEMS end-use device, wherein the IC die includes:
a plurality of solder balls on a planar surface of the IC die;
a plurality of wire bond pads on the planar surface; and
one or more conductor paths interconnecting one or more of the plurality of solder balls with one or more of the plurality of wire bond pads, wherein the one or more conductor paths interconnect the one or more solder balls and the one or more wire bond pads such that either the plurality of solder balls or the plurality of wire bond pads are configured to be used to test the IC die, and wherein the plurality of solder balls or the plurality of wire bond pads not configured to be used to test the IC die connect the IC die to the MEMS end-use device.
11. The apparatus of claim 10, wherein the plurality of solder balls comprise a solder ball array.
12. The apparatus of claim 10, wherein the plurality of solder balls comprise flip-chip controlled-collapse chip connections.
13. The apparatus of claim 10, wherein the one or more conductor paths comprise discrete conductor paths.
14. The apparatus of claim 10, wherein the IC die is a known good die, and wherein the plurality of solder balls or the plurality of wire bond pads configured to be used to test the IC die are non-pristine and unusable for connecting to the MEMS end-use device.
15. The apparatus of claim 14, wherein the plurality of solder balls are non-pristine, and wherein the non-pristine solder balls include one or more distorted solder balls.
16. The apparatus of claim 15, wherein the distorted solder balls include one or more reflown solder balls.
17. The apparatus of claim 15, wherein the distorted solder balls include one or more solder balls having a taffy-pull configuration.