Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device is provided with a semiconductor substrate, a plurality of active regions separated from each other by element isolation regions formed on the semiconductor substrate; gate oxide films formed on the active regions; gate electrodes formed on the gate oxide films; side wall insulation films formed on side surfaces of the gate electrodes; recessed parts formed in exposed surfaces of the active regions excluding regions that are covered by the gate electrodes and the side wall insulation films; dam insulation films provided to a periphery of the recessed parts; and silicon epitaxial layers formed within the recessed parts.
1. A method, comprising:
selectively forming an isolation region in a semiconductor substrate to define a memory array region and a peripheral circuit region, the memory array region including a first active region for a memory cell transistor of a first channel type, the peripheral circuit region including second and third active regions respectively for first and second peripheral transistors, the first peripheral transistor being of the first channel type, the second peripheral transistor being of a second channel type that is different from the first channel type, each of the first, second, and third active regions including a channel formation portion and source and drain formation portions;
forming a first gate structure on the channel formation portion of the first active region and second and third gate structures respectively on the channel formation portions of the second and third active regions, the first gate structure being for the memory cell transistor, the second gate structure being for the first peripheral transistor, the third gate structure being for the second peripheral transistor, each of the first, second, and third gate structures comprising a gate insulating film and a gate electrode formed on the gate insulating film;
removing respective parts of the source and drain formation portions of the first active region to form recesses respectively in the source and drain formation portions of the first active region, the removing the respective parts of the source and drain formation portions of the first active region being carried out while protecting respective parts of the source and drain formation portions of the second and third active regions from being removed; and
performing epitaxial growth to form epitaxial layers in the recesses of the source and drain formation portions of the first active regions and on the source and drain formation regions of each of the second and third active regions.
2. The method as claimed in claim 1 , wherein the first channel type is an N channel type and the second channel type is a P channel type.
3. The method as claimed in claim 1 , wherein each of the first, second, and third gate structures further comprises sidewall insulating films formed on respective side walls of the gate electrode, and the removing the respective parts of the source and drain formation portions of the first active region is carried out by using the first gate structure as a mask.
4. The method as claimed in claim 1 , further comprising:
introducing first impurities in the source and drain regions of the first and second active regions to form source and drain regions of the memory cell transistor and the first peripheral transistor while masking the third active region; and
introducing second impurities in the source and drain regions of the third active region to form source and drain regions of the second peripheral transistor while masking the first and second active regions;
each of the introducing the first impurities and the introducing the second impurities being carried out prior to the removing the respective parts of the source and drain formation portions of the first active region.
5. The method as claimed in claim 4 , further comprising:
introducing third impurities in the epitaxial layers formed in the recesses of the source and drain regions of the first active region and on the source and drain regions of the second active
region while masking the third active region; and
introducing fourth impurities in the epitaxial layers formed on the source and drain regions of the third active region while masking the first and second active regions.