IP Library Granted Patent US 7,768,279
Granted Patent B2
US 7,768,279 · App. 11/812,648 · Granted Aug 3, 2010

Control method and control program for prober

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 7,768,279
App. No.
11/812,648
Granted
Aug 3, 2010
Kind
B2
Abstract

To provide a control method and a control program of a prober that are capable of enhancing throughput. Chips are tested in step S 2 . In step S 3 , when the counted number Y of conforming chips has reached a predetermined number of conforming chips X which constitutes conditions for testing, the process advances to step S 10 . In step S 10 , testing of wafers taking place at that time is interrupted, and this wafer is stored in an output cassette OC 1 . In a subsequent step S 11 , the subsequent wafer is tested, and stored in the output cassette OC 2 (step S 12 ). When all wafers have been tested, the process advances to step S 14 , and testing of the lot is completed. As a result, wafers that remain untested and wafers that have been tested stored separately in the input cassette and the output cassettes.

Claims (29)

1. A control method for a prober that tests a plurality of semiconductor devices manufactured on a semiconductor wafer, comprising:

taking out from a first storage unit in which a plurality of semiconductor wafers that are to be tested are stored one of semiconductor wafers that is subject to testing, and testing the semiconductor devices on the one of the semiconductor wafers sequentially,

detecting, during the testing, whether or not results of testing satisfy conditions for testing that have been set in advance, and

storing in a second storage unit the one of the semiconductor wafers on which the semiconductor device have been tested,

wherein the taking, the testing and the storing are repeated, and

in the storing, on the basis of a detection of the conditions by the detecting, the second storage unit in which the semiconductor wafer is stored is exchanged for another storage unit.

2. The control method for a prober according to claim 1 , further comprising:

detecting when results of testing have satisfied conditions for testing that have been set in advance,

wherein on the basis of the detection testing of the semiconductor wafer is interrupted in midstream.

3. The control method for a prober according to claim 2 , wherein the condition for testing is the number of conforming items that pass the testing of the semiconductor devices.

4. The control method for a prober according to claim 2 , wherein on the basis of the detection, results of testing the semiconductor wafers stored in the second storage unit are output.

5. The control method for a prober according to claim 1 ,

wherein the second storage unit includes a plurality of storage units.

6. The control method for a prober according to claim 1 , wherein the condition for testing is the number of semiconductor wafers that have been tested.

7. The control method for a prober according to claim 1 , wherein the condition for testing is the number of conforming items that pass the testing of the semiconductor device.

8. The control method for a prober according to claim 1 , wherein on the basis of the detection, results of testing semiconductor wafers stored in the second storage unit are output.

9. A control method for a prober that tests a plurality of semiconductor devices manufactured on a semiconductor wafer, comprising:

taking out from a first storage unit in which a plurality of semiconductor wafers that are to be tested are stored one of semiconductor wafers that is subject to testing, and testing the semiconductor devices on the one of the semiconductor wafers sequentially,

detecting, during the testing, whether or not results of testing satisfy conditions for testing that have been set in advance, and

storing in a second storage unit the one of the semiconductor wafers on which the semiconductor device have been tested,

wherein the taking, the testing and the storing are repeated,

on the basis of a detection by the detecting, testing of the semiconductor device on the one of the semiconductor wafers is interrupted in midstream, and

upon semiconductor devices are becoming present on the semiconductor wafer that remained untested at a time that the testing was interrupted, dummy test results are assigned to the semiconductor devices that remain untested.

10. A tangible computer readable medium having computer-executable instructions adapted thereon that, when executed by a processor, perform a method for a prober for testing a plurality of semiconductor devices manufactured on a semiconductor wafer, the method comprising:

taking out from a first storage unit in which a plurality of semiconductor wafers that are to be tested are stored one of semiconductor wafers that is subject to testing, and testing the semiconductor devices on the one of the semiconductor wafers sequentially,

detecting, during the testing, whether or not results of testing satisfy conditions for testing that have been set in advance, and

storing in a second storage unit the one of the semiconductor wafers on which the semiconductor devices have been tested,

wherein the taking, the testing and the storing are repeated, and

in the storing, on the basis of a detection of the conditions by the detecting, the second storage unit in which the semiconductor wafer is stored is exchanged for another storage unit.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
CHANGE OF NAME Recorded Sep 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 025046/0478 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2007
From: ONO, YASUKAZU
To: FUJITSU LIMITED
Reel/Frame 019508/0907 →
Priority Claims (1)
JP 2006-177015 · Jun 27, 2006 · national
Continuity (1)
Related Publication 20070296430A1 · Dec 27, 2007