Ceramic wiring board and process for producing the same, and semiconductor device using the same
View Patent ↗A ceramic wiring board 10 includes a ceramic substrate 11 and a wiring layer 12 formed on the ceramic substrate 11 . The wiring layer 12 includes a wiring part 13 and a connection part 14 , the wiring part 13 having a base metal layer 15 , a first diffusion preventive layer 16 and a first Au layer 17 which are stacked in sequence on a surface of the ceramic substrate 11 , and the connection part 14 having a second diffusion preventive layer 19 , a void suppression layer 20 and a solder layer 18 which are stacked in sequence at a desired position on the wiring part 13 . The void suppression layer 20 is made of, for example, Au or an Au—Sn alloy containing 85 mass % or more of Au.
1. A ceramic wiring board, comprising:
a ceramic substrate; and
a wiring layer including a wiring part and a connection part formed on the wiring part, the wiring part having a base metal layer, made of at least one selected from Ti, Zr, Hf, Nb, Cr, Ta, Ni, a Ti-based alloy, a Ta-based alloy, and a Ni-based alloy, a first diffusion preventive layer made of at least one selected from Pt, Pd, Ni, a Pt-based alloy, a Pd-based alloy, and a Ni-based alloy and a first Au layer which are stacked in sequence on a surface of the ceramic substrate, and the connection part having a second diffusion preventive layer, made of at least one selected from Pt, Pd, Ni, a Pt-based alloy, a Pd-based alloy, and a Ni-based alloy, a void suppression layer made of Au or an Au—Sn alloy containing 85 mass % or more of Au and a solder layer containing at least Sn which are stacked in sequence,
wherein the void suppression layer has a thickness in a range of not less than 30 nm nor more than 500 nm, the first diffusion preventive layer has a thickness in a range of not less than 0.1 μm nor more than 0.4 μm, and the second diffusion preventive layer has a thickness in a range of not less than 0.05 μm nor more than 1 μm.
2. The ceramic wiring board according to claim 1 , wherein the solder layer is made of a Sn alloy containing at least one selected from Au, Ag, Al, Bi, Cu, Cr, Ga, Ge, Ni, Pt, Si, Ti, and Zn.
3. The ceramic wiring board according to claim 1 , wherein the second diffusion preventive layer has a wider width than the solder layer.
4. The ceramic wiring board according to claim 3 , wherein the second diffusion preventive layer has a shape with an outer peripheral portion thereof protruding from an end portion of the solder layer by an amount in a range not less than 1 μm nor more than 100 μm.
5. The ceramic wiring board according to claim 1 , wherein the connection part has a third Au layer formed on the solder layer.
6. A semiconductor device, comprising: the ceramic wiring board according to claim 1 ; and a semiconductor element electrically and mechanically connected onto the wiring layer of the ceramic wiring board via the solder layer.
7. The semiconductor device according to claim 6 , wherein the semiconductor element is an optical semiconductor element.
8. The ceramic wiring board according to claim 1 , wherein the ceramic substrate comprises an aluminum nitride sintered compact.
9. A system comprising a ceramic wiring board, wherein the ceramic wiring board comprises:
a ceramic substrate; and
a wiring layer including:
a wiring portion; and
a connection portion formed over the wiring portion;
wherein the wiring portion comprises:
a base metal layer comprising at least one of Ti, Zr, Hf, Nb, Cr, Ta, Ni, a Ti-based alloy, a Ta-based alloy, or a Ni-based alloy;
a first diffusion preventive layer comprising at least one of Pt, Pd, Ni, a Pt-based alloy, a Pd-based alloy, or a Ni-based alloy; and
a first Au layer;
wherein the base metal layer, the first diffusion layer, and the first Au layer are stacked in sequence over a surface of the ceramic substrate;
wherein the connection portion comprises:
a second diffusion preventive layer comprising at least one of Pt, Pd, Ni, a Pt-based alloy, a Pd-based alloy, or a Ni-based alloy;
a void suppression layer comprising Au or an Au—Sn alloy containing 85 mass % or more of Au; and
a solder layer comprising Sn;
wherein the second diffusion preventive layer, the void suppression layer, and the solder layer are stacked in sequence; and
wherein the void suppression layer has a thickness between 30 nm and 500 nm, the first diffusion preventive layer has a thickness between 0.1 μm and 0.4 μm, and the second diffusion preventive layer has a thickness between 0.05 μm and 1 μm.
10. The system of claim 9 , wherein the ceramic substrate comprises one of an aluminum nitride, a silicon nitride, an aluminum oxide, or a silicon carbide.
11. The system of claim 9 , wherein the second diffusion preventive layer has a wider width than the solder layer, and wherein the second diffusion preventive layer has a shape with an outer peripheral portion thereof protruding from an end portion of the solder layer by an amount of between 1 μm and 100 μm.
12. The system of claim 9 , further comprising a semiconductor element electrically and mechanically coupled to the wiring layer of the ceramic wiring board via the solder layer.