Nonvolatile semiconductor memory device for writing multivalued data
A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching.
1. A nonvolatile semiconductor memory device comprising:
a memory array including a plurality of nonvolatile memory cells arranged in rows and columns, and each storing a logical value of N bits according to a threshold voltage;
a selecting circuit selecting a memory cell as a write target from said memory array;
a memory array sense amplifier operating to provide the logical value of N bits stored in the selected memory cell;
a first buffer having N bits each storing a write target value for a corresponding memory cell;
a second buffer storing a value determining processing to be effected on a corresponding memory cell;
a write driver selecting application of a write pulse when the bit in the second buffer corresponding to said selected memory cell indicates a first value; and
a verify circuit comparing a logical value of the N bits provided from said memory array sense amplifier with the write target value of the corresponding N bits in said first buffer, providing a signal indicating success of a verify operation when a result of the comparison indicates matching, and providing a signal indicating failure of the verify operation when a result of the comparison indicates mismatching, wherein
when the result of comparison indicates the matching, and the bit in said second buffer corresponding to said selected memory cell indicates the first value, said verify circuit changes the said bit in said second buffer to indicate a second value; and
wherein said verify circuit transfers said second value to the bit in said second buffer prior to upper foot verify when a corresponding memory cell stores said write target value corresponding to a range of a minimum threshold voltage of the selected memory cell, and said verify circuit provides a signal indicating the verify “pass” during the upper foot verify even when the result of said comparison represents mismatching, if the bit in said second buffer corresponding to the logical value of the N bits to be compared takes the second value.