Electrostatic discharge protection circuit and terminating resistor circuit
View Patent ↗Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
1. An electrostatic discharge protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising:
a pair of transistors connected to each of two lines which are connected to external terminals of the semiconductor device and through which differential signals propagate, the pair of transistors being formed in the same well so as to clamp the electrostatic discharge applied to the external terminals wherein the lines are constituted by a pair of transmission lines, and wherein characteristic impedances of branched transmission lines connected to the pair of transistors from the pair of transmission lines are equal to or smaller than characteristic impedances of the pair of transmission lines.
2. An electrostatic discharge protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising:
a pair of transistors connected to each of two lines which are connected to external terminals of the semiconductor device and through which differential signals propagate, the pair of transistors being formed in the same well so as to clamp the electrostatic discharge applied to the external terminals, wherein the lines are constituted by a pair of transmission lines, and wherein on-resistances of the pair of transistors are equal to or smaller than characteristic impedances of the pair of transmission lines.
3. An electrostatic discharge protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising:
a pair of transistors connected to each of two lines which are connected to external terminals of the semiconductor device and through which differential signals propagate, the pair of transistors being formed in the same well so as to clamp the electrostatic discharge applied to the external terminals, wherein the pair of transistors are connected to a power supply/ground pair transmission line having a characteristic impedance equal to or smaller than on-resistances of the pair of transistors.
4. An electrostatic discharge protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising:
a pair of transistors connected to each of two lines which are connected to external terminals of the semiconductor device and through which differential signals propagate, the pair of transistors being formed in the same well so as to clamp the electrostatic discharge applied to the external terminals, wherein a distance between drain diffusion regions of the pair of transistors is determined such that a transfer time of charges which transfer between the drain diffusion regions is shorter than a transition time of the differential signals.
5. An electrostatic discharge protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising:
a pair of transistors connected to each of two lines which are connected to external terminals of the semiconductor device and through which differential signals propagate, the pair of transistors being formed in the same well so as to clamp the electrostatic discharge applied to the external terminals, wherein the pair of transistors clamps the electrostatic discharge to one or both of a power supply and ground, and wherein the pair of transistors for clamping the electrostatic discharge to the power supply are formed in the same well and another pair of transistors for clamping the electrostatic discharge to the ground are formed in the same well.
6. An electrostatic discharge protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising:
a pair of transistors connected to each of two lines which are connected to external terminals of the semiconductor device and through which differential signals propagate, the pair of transistors being formed in the same well so as to clamp the electrostatic discharge applied to the external terminals, wherein in the pair of transistors, gates are formed in parallel, first sources and drains of the pair of transistors are formed on the side where the gates face to each other, and each second source of the pair of transistors is formed on the side opposite the first sources and the drains across each of the gates.