System for retaining state data of an integrated circuit
According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
1. A system for retaining M bits of state data of an integrated circuit during power down, said system comprising:
M serially coupled scan flip flops divided into M/N groups, each of said groups containing a merged scan flip flop and a final scan flip flop, said M serially coupled scan flip flops containing said M bits of state data;
said merged scan flip flop in each of said groups being coupled to a respective read port of a memory unit, and said final scan flip flop of each of said groups being coupled to a respective write port of said memory unit, said system thereby enabling said memory unit to save said M bits of state data in N clock cycles;
wherein said M serially coupled scan flip flops are powered by a first power supply and wherein said memory unit is powered by a second power supply.
2. The system of claim 1 wherein said system enables said memory unit to restore said M bits of state data to said M serially coupled scan flip flops in N clock cycles.
3. The system of claim 1 wherein said M serially coupled scan flip flops are situated in said integrated circuit.
4. The system of claim 1 wherein each of said M serially coupled scan flip flops includes a scan input and a corresponding scan output.
5. The system of claim 1 wherein said memory unit is a static random access memory (“SRAM”) configured to save N M/N bit words.
6. The system of claim 1 wherein said system is controlled by a standby signal.
7. The system of claim 1 wherein said integrated circuit is a CPU situated in a portable electronic device.
8. The system of claim 7 wherein said portable electronic device is selected from the group consisting of a cellular telephone, a personal digital assistant (“PDA”), a laptop computer, and MP3 player, and a digital camera.
9. A state data retaining system for retaining M bits of said state data of an integrated circuit during power down, said state data retaining system comprising:
M flip flops divided into M/N groups, each of said M/N groups containing a plurality of grouped flip flops, said M flip flops configured to contain said M bits of said state data;
each of said plurality of grouped flip flops being coupled to a respective read port of a memory unit, said state data retaining system thereby enabling said memory unit to save said M bits of said state data of said integrated circuit in N clock cycles,
wherein said M flip flops are powered by a first power supply and wherein said memory unit is powered by a second power supply.
10. The state data retaining system of claim 9 wherein said state data retaining system enables said memory unit to restore said M bits of said state data to said M flip flops in N clock cycles upon power up.
11. The state data retaining system of claim 9 wherein said M flip flops are situated in said integrated circuit.
12. The state data retaining system of claim 9 wherein each of said M flip flops includes a scan input and a corresponding scan output.
13. The state data retaining system of claim 9 wherein said memory unit is a static random access memory (“SRAM”) configured to save N M/N bit words.
14. The state data retaining system of claim 9 wherein said system is controlled by a standby signal.
15. The state data retaining system of claim 9 wherein said integrated circuit is a CPU situated in a portable electronic device.
16. The state data retaining system of claim 15 wherein said portable electronic device is selected from the group consisting of a cellular telephone, a personal digital assistant (“PDA”), a laptop computer, an MP3 player, and a digital camera.