Image processing circuit, image processing system and method therefor
Each functional block constituting a pipeline resets its own memory device in synchronization with a timing that last pixel data of one line is processed and output. A reset controlling unit in a first functional block includes an attribute signal generation circuit for generating an attribute signal indicating whether or not each pixel data being input is last pixel data and attaches this attribute signal to the pixel data by transferring in synchronization with corresponding pixel data. When the processed pixel data is output, the attribute signal of the corresponding pixel data is referred to control resetting the memory device. Other functional blocks control resetting their own memory devices using an attribute signal synchronized with the pixel data and transferred from previous functional block.
1 . An image processing circuit to sequentially process each pixel data constituting one line, the image processing circuit comprising:
a plurality of memory devices each holding the pixel data being sequentially input;
a processing unit to process pixel data held by a predetermined memory device among the plurality of memory devices; and
a reset controlling unit to reset the plurality of memory devices in synchronization with a timing of last pixel data of the one line being processed and output by the processing unit.
2 . The image processing circuit according to claim 1 , wherein the processing unit performs a process using each pixel data held in the plurality of continuous memory devices.
3 . The image processing circuit according to claim 2 , wherein at first pixel data of one line being held to a predetermined memory device among the plurality of continuous memory devices, pixel data processed using the first pixel data is stored from the predetermined memory device to the memory device in a direction of process.
4 . The image processing circuit according to claim 2 , wherein the processing unit holds pixel data in a memory device of a next stage and repeats this process sequentially, the pixel data being the processed pixel data held in the memory device.
5 . The image processing circuit according to claim 2 , wherein the processing unit is controlled by a signal synchronized with a timing first or last pixel data of the one line sequentially transfers the memory device.
6 . The image processing circuit according to claim 1 , wherein the reset controlling unit refers to an attribute signal to control resetting the memory device, the attribute signal being generated when last pixel data is input to the processing unit and transferred in synchronization with a timing the pixel data is transferred to the memory device.
7 . The image processing circuit according to claim 6 , wherein the reset controlling unit comprises:
an input pixel counter to count the number of pixel data being input with a start point as first pixel data of one line; and
a comparator to compare the counted number by the counter with a total number of pixel data in the one line,
wherein for pixel data being input at an indication by the comparison result of the comparator showing a match, an attribute signal is generated indicating the pixel data is last pixel data.
8 . An image processing system comprising:
a plurality of the image processing circuits of claim 1 being connected in order for a lower image processing circuit to sequentially processes pixel data output from an adjacent upper image processing circuit.
9 . The image processing system according to claim 8 , wherein to each pixel data being input, the reset controlling unit in a top image processing circuit generates and attaches an attribute signal indicating whether or not the pixel data is last pixel data and at an output of the processed pixel data, the reset controlling unit refers to the attribute signal of the pixel data so as to control the reset, and
the reset controlling unit in other image processing circuit refers to the attribute signal attached to the pixel data at an output of pixel data by the image processing circuit so as to control the reset.
10 . The image processing circuit according to claim 9 , wherein the reset controlling unit in the top image processing circuit comprises:
an input pixel counter to count the number of pixel data being input with a start point as first pixel data of one line; and
a comparator to compare the counted number by the input pixel counter with a total number of pixel data in the one line,
wherein for pixel data being input at an indication of the comparison result of the comparator shows the both numbers match, an attribute signal is generated indicating the pixel data is last pixel data.
11 . The image processing circuit according to claim 1 , wherein the reset controlling unit comprises:
an output pixel counter to count the number of pixel data being processed and output with a start point as first pixel data of one line; and
a comparator to compare the counted number by the output pixel counter with a total number of pixel data in the one line,
wherein the reset is performed at an indication the comparison result of the comparator shows a match.
12 . An image processing system comprising:
a plurality of the image processing circuits according to claim 11 being connected in order for a lower image processing circuit to sequentially processes pixel data output from an adjacent upper image processing circuit.
13 . An image processing circuit to sequentially process each pixel data constituting one line, the image processing circuit comprising:
a controlling unit to generate and attaches an attribute signal to each of the pixel data being input, the attribute signal indicating whether or not the pixel data is first pixel data or last pixel data.
14 . An image processing system comprising:
a plurality of image processing circuits being connected to sequentially process each pixel data constituting one line in order for a lower image processing circuit to sequentially process pixel data output from an adjacent upper image processing circuit,
wherein a top image processing circuit is the image processing circuit of claim 13 .
15 . A method to process image to sequentially process each pixel data constituting one line, the method comprising:
holding the pixel data sequentially input in a plurality of memory devices in order of input;
processing and outputting pixel data held in a predetermined memory device among the plurality of memory devices; and
resetting the plurality of memory devices in synchronization with a timing last pixel data of the one line is processed and output.
16 . The method according to claim 15 , further comprising:
performing a process using each pixel data held in the plurality of continuous memory devices.
17 . The method according to claim 15 , further comprising:
generating and attaching to each pixel data being input, an attribute signal indicating the pixel data is last pixel data; and
performing the reset at an indication of the attribute signal for pixel data showing to be last pixel data in outputting the processed pixel data.
18 . The method according to claim 17 , further comprising:
counting the number of pixel data being input with a start point as first pixel data of one line;
comparing the counted number with a total number of pixel data in the one line; and
generating an attribute signal indicating pixel data to be last pixel data for the pixel data being input at an indication of the comparison result showing a match.
19 . The method according to claim 15 , which is processed in each processing circuit of an image processing system including a plurality of the image processing circuit being connected to sequentially process each pixel data constituting one line in order for a lower image processing circuit to sequentially process pixel data output from an adjacent upper image processing circuit.
20 . The method according to claim 19 , further comprising:
performing a process using each pixel data held in the plurality of continuous memory devices.
21 . The method according to claim 19 , wherein in a top image processing circuit, for each pixel data being input, an attribute signal indicating whether or not the pixel data is last pixel data is generated and attached and in outputting processed pixel data, the reset is performed at an indication of the attribute signal for the pixel data being the last pixel data, and
in other image processing circuit, in outputting pixel data processed by the image processing circuit, the reset is performed at an indication of the attribute signal for the pixel data being the last pixel data.
22 . The method according to claim 15 , further comprising:
counting the number of pixel data being input with a start point as first pixel data of one line; and
comparing the counted number with a total number of pixel data in the one line,
wherein the reset is performed at an indication of the comparison result showing a match.
23 . The method according to claim 19 , further comprising:
counting the number of pixel data being input with a start point as first pixel data of one line; and
comparing the counted number with a total number of pixel data in the one line,
wherein the reset is performed at an indication of the comparison result showing a match.
24 . A method to process image to sequentially process each pixel data constituting one line, the method comprising:
generating and attaching an attribute signal to each of the pixel data being input, the attribute signal indicating whether or not the pixel data is first pixel data or last pixel data.
25 . A method to process image in an image processing system including a plurality of image processing circuits being connected to sequentially process each pixel data constituting one line in order for a lower image processing circuit to sequentially process pixel data output from an adjacent upper image processing circuit, the method comprising:
generating and attaching in a top image processing circuit an attribute signal to each of the pixel data being input, the attribute signal indicating whether or not the pixel data is first pixel data or last pixel data.