IP Library Patent Application 11822133
Patent Application
App. No. 11/822,133

Method and computer program product for circuit analysis and circuit simulation device

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Patent No.
US None
App. No.
11/822,133
Abstract

A method and a computer program product for a circuit analysis and a circuit simulation device, capable of increasing an analysis speed for circuit analysis, the circuit simulation device includes a circuit matrix generation unit for generating a coefficient matrix based on netlist information corresponding to a circuit to be analyzed, a fill-in parameter counting unit for acquiring a fill-in parameter for the coefficient matrix, an analysis selection unit for selecting either of the direct method or the iterative method as a solution-producing method for the coefficient matrix based on the fill-in parameter, a matrix size of the coefficient matrix and number of non-zero elements of the coefficient matrix and analyzing units for producing a solution of the coefficient matrix as an analysis result of the circuit by a selected one of the direct method and the iterative method.

Claims (26)

1 . A circuit analysis method comprising:

acquiring netlist information corresponding to a circuit to be analyzed;

generating a coefficient matrix corresponding to a circuit equation of the circuit based on the netlist information;

acquiring a fill-in parameter for the coefficient matrix;

selecting either a direct method or an iterative method as a solution-producing method for the coefficient matrix based on the fill-in parameter, a matrix size of the coefficient matrix and number of non-zero elements of the coefficient matrix; and

producing a solution for the coefficient matrix as analysis result of the circuit by a selected one of the direct method and the iterative method.

2 . The circuit analysis method according to claim 1 , wherein the acquiring the fill-in parameter includes:

performing an advance elimination for the coefficient matrix; and

acquiring the fill-in parameter by counting number of matrix elements filled in the coefficient matrix.

3 . The circuit analysis method according to claim 1 , further including:

estimating the fill-in parameter, the matrix size and the number of non-zero elements by a directed graph based on the netlist information, wherein the selecting the solution-producing method selects either of the direct method or the iterative method based on the estimated fill-in parameter, the estimated matrix size and the estimated number of non-zero elements.

4 . The circuit analysis method according to claim 1 , further including:

setting a solution-producing method selection condition as a predetermined value, wherein the selecting the solution-producing method includes:

selecting the iterative method as the solution-producing method if (a+b) 2 /(a×N)>Fill is satisfied, wherein “a” is the number of non-zero elements, “b” is the fill-in parameter, “N” is the matrix size and “Fill” is the solution-producing method selection condition.

5 . The circuit analysis method according to claim 4 , wherein the selecting the solution-producing method includes:

selecting the direct method as the solution-producing method if (a+b) 2 /(a×N)<Fill is satisfied.

6 . A computer program product embodied on a computer-readable medium and comprising code that, when executed, causes computer to perform the steps of the method according to claim 1 .

7 . A circuit simulation device comprising:

a circuit matrix generation unit for generating a coefficient matrix based on netlist information corresponding to a circuit to be analyzed;

a fill-in parameter counting unit for acquiring a fill-in parameter for the coefficient matrix;

an analysis selection unit for selecting either a direct method or an iterative method as a solution-producing method for the coefficient matrix based on the fill-in parameter, a matrix size of the coefficient matrix and number of non-zero elements of the coefficient matrix; and

an analyzing unit for producing a solution for the coefficient matrix as an analysis result of the circuit by a selected one of the direct method and the iterative method.

8 . The circuit simulation device according to claim 7 , further including a computing time estimating unit for estimating the fill-in parameter, the matrix size and the number of non-zero elements based on the netlist information.

9 . The circuit simulation device according to claim 8 , wherein the computing time estimating unit estimates the fill-in parameter, the matrix size and the number of non-zero elements by a directed graph based on the netlist information.

10 . The circuit simulation device according to claim 7 , further including a storage unit for storing a solution-producing method selection condition as a predetermined value, wherein the analysis selection unit selects the iterative method as the solution-producing method if (a+b) 2 /(a×N)>Fill is satisfied and the analyzing unit produces a solution for the coefficient matrix by the iterative method, wherein “a” is the number of non-zero elements, “b” is the fill-in parameter, “N” is the matrix size and “Fill” is the solution-producing method selection condition.

11 . The circuit simulation device according to claim 10 , wherein the analysis selection unit selects the direct method as the solution-producing method if (a+b) 2 /(a×N)<Fill is satisfied and the analyzing unit produces a solution for the coefficient matrix by the direct method.

Assignments (2)
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0456 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2007
From: KUWADA, KIMIHIKO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 019574/0959 →