Display controller in display device, and method of transferring display data
A display controller comprising: a memory in which a display data is stored; a driver configured to drive a display panel in response to the display data; and a clock generation circuit configured to generate a clock that is used for transferring the display data from the memory to the driver. The generated clock is fed back to adjust a clock frequency of the clock.
1 . A display controller comprising:
a memory in which a display data is stored;
a driver configured to drive a display panel in response to said display data; and
a clock generation circuit configured to generate a clock that is used for transferring said display data from said memory to said driver,
wherein said generated clock is fed back to adjust a clock frequency of said clock.
2 . The display controller according to claim 1 ,
wherein said clock generation circuit monitors said generated clock, and adjusts said clock frequency such that a frequency of said monitored clock is corrected to a predetermined frequency.
3 . The display controller according to claim 2 ,
wherein said clock generation circuit generates said clock at a first frequency,
wherein said clock generation circuit calculates a ratio between said frequency of said monitored clock and said predetermined frequency, and corrects said first frequency by using said calculated ratio.
4 . The display controller according to claim 1 ,
wherein said clock generation circuit monitors said generated clock, and adjusts said clock frequency such that a number of pulses of said monitored clock within a predetermined period is corrected to a predetermined value.
5 . The display controller according to claim 4 ,
wherein said clock generation circuit generates said clock at a first frequency,
wherein said clock generation circuit calculates a ratio between said number of pulses within said predetermined period and said predetermined value, and corrects said first frequency by using said calculated ratio.
6 . The display controller according to claim 5 ,
wherein said clock generation circuit includes:
an oscillator configured to generate said clock at said first frequency;
a counter configured to count a number of pulses of said generated clock within said predetermined period; and
a control circuit configured to change said first frequency based on said ratio between said number of pulses within said predetermined period and said predetermined value set in a register.
7 . The display controller according to claim 4 ,
wherein said predetermined period corresponds to one line period during which said display data is transferred.
8 . The display controller according to claim 1 ,
wherein said adjustment of said clock frequency is performed in a non-display period during which an image corresponding to said display data is not displayed on said display panel.
9 . The display controller according to claim 4 ,
wherein said clock generation circuit adjusts said clock frequency in a non-display period during which an image corresponding to said display data is not displayed on said display panel.
10 . The display controller according to claim 9 ,
wherein in other than said non-display period, said clock generation circuit stops generating said clock when said number of pulses within said predetermined period becomes equal to said predetermined value.
11 . The display controller according to claim 9 ,
wherein said clock generation circuit interrupts generation of said clock at a specified timing during said predetermined period.
12 . The display controller according to claim 8 ,
wherein said non-display period corresponds to an initial line of a frame.
13 . The display controller according to claim 9 ,
wherein said non-display period corresponds to an initial line of a frame.
14 . A method of transferring a display data in a display device which includes a memory storing a display data and a driver driving a display panel in response to said display data, comprising:
(A) generating a clock that is used for transferring said display data from said memory to said driver;
(B) transferring said display data by using said generated clock;
(C) counting a number of pulses of said generated clock within a predetermined period; and
(D) adjusting a clock frequency of said clock such that said number of pulses within said predetermined period is corrected to a predetermined value.
15 . The method according to claim 14 ,
wherein said predetermined period corresponds to a period of said (B) step.
16 . The method according to claim 14 ,
wherein said (D) step is performed in a non-display period during which an image corresponding to said display data is not displayed on said display panel.
17 . The method according to claim 16 ,
wherein said non-display period corresponds to an initial line of a frame.
18 . The method according to claim 16 , further comprising:
(E) after said (D) step, repeating said (A) to (C) steps by using said adjusted clock frequency.
19 . The method according to claim 18 , further comprising:
(F) in said (E) step, stopping generation of said clock when said number of pulses within said predetermined period becomes equal to said predetermined value.
20 . The method according to claim 14 , further comprising:
(G) interrupting generation of said clock at a specified timing during said predetermined period.