Semiconductor memory device
View Patent ↗A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
1. A semiconductor memory device, comprising:
a memory cell array;
an address control circuit block configured to perform an access control to the memory cell array;
a data I/O circuit block configured to transmit and receive data to and from the memory cell array;
a mode register;
a main control circuit changing at least one of the address control circuit block and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to the mode register;
a main power supply wiring configured to supply a power to the address control circuit block and the data I/O circuit block; and
a pseudo power supply wiring configured to correspond to each of the address control circuit block and the data I/O circuit block, wherein
the main control circuit is configured to disconnect the pseudo power supply wiring from the main power supply wiring if a corresponding one of the address control circuit block and the data I/O circuit block is in the standby state, and to connect the pseudo power supply wiring to the main power supply wiring if the corresponding one of the address control circuit block and the data I/O circuit block is in the active state.
2. A semiconductor memory device, comprising:
a memory cell array;
an address control circuit block configured to perform an access control to the memory cell array;
a data I/O circuit block configured to transmit and receive data to and from the memory cell array;
a mode register;
a main control circuit configured to change at least one of the address control circuit block and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to the mode register, wherein
the predetermined mode signal is a mode signal for entering a predetermined operation mode using a data input-output terminal, and
the main control circuit is configured to change the data I/O circuit block from the standby state into the active state while keeping the address control circuit block in the standby state in response to the setting of the predetermined operation mode to the mode register.
3. The semiconductor memory device as claimed in claim 1 ,
wherein the predetermined mode signal is a mode signal for entering a predetermined operation mode using a data input-output terminal, and
wherein the main control circuit changes the data I/O circuit block from the standby state into the active state while keeping the address control circuit block in the standby state in response to the setting of the predetermined operation mode to the mode register.
4. The semiconductor memory device as claimed in claim 2 , wherein the predetermined operation mode includes at least one of an ODT operation mode and an OCD-impedance adjustment mode.
5. A data processing system comprising a data processor and a semiconductor memory device, wherein the semiconductor memory device includes:
a memory cell array;
an address control circuit block configured to perform an access control to the memory cell array;
a data I/O circuit block configured to transmit and receive data to and from the memory cell array;
a mode register; and
a main control circuit configured to change the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to the mode register while keeping the address control circuit in the standby state.
6. A semiconductor memory device comprising:
a memory cell array;
an address control circuit block configured to perform an access control to the memory cell array;
a data I/O circuit block configured to transmit and receive data to and from the memory cell array;
a mode register; and
a main control circuit configured to change the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to the mode register while keeping the address control circuit block in the standby state.
7. The semiconductor memory device as claimed in claim 6 , further comprising:
a main power supply wiring configured to supply a power to the address control circuit block and the data I/O circuit block; and
a pseudo power supply wiring configured to correspond to each of the address control circuit block and the data I/O circuit block, wherein
the main control circuit is further configured to disconnect the pseudo power supply wiring from the main power supply wiring if a corresponding one of the address control circuit block and the data I/O circuit block is in the standby state, and to connect the pseudo power supply wiring to the main power supply wiring if the corresponding one of the address control circuit block and the data I/O circuit block is in the active state.
8. The semiconductor memory device as claimed in claim 6 , wherein
the predetermined mode signal is a mode signal for entering a predetermined operation mode using a data input-output terminal, and
the main control circuit is configured to change the data I/O circuit block from the standby state into the active state while keeping the address control circuit block in the standby state in response to the setting of the predetermined operation mode to the mode register.
9. The semiconductor memory device as claimed in claim 6 , wherein the predetermined operation mode includes at least one of an ODT operation mode and an OCD-impedance adjustment mode.
10. The semiconductor memory device as claimed in claim 7 , wherein the predetermined operation mode includes at least one of an ODT operation mode and an OCD-impedance adjustment mode.
11. The semiconductor memory device as claimed in claim 8 , wherein the predetermined operation mode includes at least one of an ODT operation mode and an OCD-impedance adjustment mode.
12. The semiconductor memory device as claimed in claim 5 , further comprising:
a main power supply wiring configured to supply a power to the address control circuit block and the data I/O circuit block; and
a pseudo power supply wiring configured to correspond to each of the address control circuit block and the data I/O circuit block, wherein
the main control circuit is further configured to disconnect the pseudo power supply wiring from the main power supply wiring if a corresponding one of the address control circuit block and the data I/O circuit block is in the standby state, and to connect the pseudo power supply wiring to the main power supply wiring if the corresponding one of the address control circuit block and the data I/O circuit block is in the active state.
13. The semiconductor memory device as claimed in claim 5 , wherein
the predetermined mode signal is a mode signal for entering a predetermined operation mode using a data input-output terminal, and
the main control circuit changes is configured to change the data I/O circuit block from the standby state into the active state while keeping the address control circuit block in the standby state in response to the setting of the predetermined operation mode to the mode register.
14. The semiconductor memory device as claimed in claim 5 , wherein
the predetermined mode signal is a mode signal for entering a predetermined operation mode using a data input-output terminal, and
the main control circuit is configured to change the data I/O circuit block from the standby state into the active state while keeping the address control circuit block in the standby state in response to the setting of the predetermined operation mode to the mode register.
15. The semiconductor memory device as claimed in claim 5 , wherein the predetermined operation mode includes at least one of an ODT operation mode and an OCD-impedance adjustment mode.