Flash memory and methods of fabricating the same
View Patent ↗Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.
1. A method for fabricating a flash memory comprising:
forming a first source in a semiconductor substrate;
forming an epitaxial layer on the semiconductor substrate;
selectively etching the epitaxial layer to form an opening at least partially exposing the first source;
sequentially forming a tunneling oxide layer, floating gates and a dielectric layer inside the opening;
forming a gate dielectric layer on the epitaxial layer;
simultaneously forming a control gate and select gates on the gate dielectric layer, the select gates being positioned at at least one distance from the opening;
forming a first drain within the epitaxial layer between the control gate and at least one of the select gates;
implanting impurities while using the control gate and the select gates as a mask to form a second source and a second drain within the epitaxial layer.
2. A method as defined in claim 1 , wherein:
the tunneling oxide layer is formed along side and bottom walls of the opening;
the floating gates are formed between the side and bottom walls of the opening; and
the dielectric layer is formed on the floating gates.
3. A method as defined in claim 2 , wherein the tunneling oxide layer is formed thicker on the bottom wall of the opening than on the sidewalls of the opening.
4. A method as defined in claim 1 , further comprising implanting impurity ions in the sidewalls of the opening while tilting the semiconductor substrate to adjust an initial threshold voltage.
5. A method as defined in claim 1 , wherein the select gates are equal in number to the floating gates.
6. A method as defined in claim 1 , wherein simultaneously forming the control gate and the select gates on the gate dielectric layer further comprises sequentially forming a polysilicon layer on the dielectric layer and selectively etching the polysilicon layer.