Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a contact point having a size of between 0.3 and 5.0 microns;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing said contact point, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a second metallization structure comprising a metal contact in said first opening.
2 . The integrated circuit chip of claim 1 , wherein said second metallization structure further comprises a third metal layer over said passivation layer, wherein said third metal layer is connected to said contact point through said metal contact.
3 . The integrated circuit chip of claim 1 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point, and wherein said second metallization structure further comprises a third metal layer on said polymer layer, said third metal layer being connected to said contact point through said metal contact.
4 . The integrated circuit chip of claim 3 , wherein said polymer layer has a thickness between 2 and 30 microns.
5 . The integrated circuit chip of claim 3 , wherein said polymer layer comprises polyimide.
6 . The integrated circuit chip of claim 3 , wherein said polymer layer comprises benzocyclobutene (BCB).
7 . The integrated circuit chip of claim 1 , wherein said second metallization structure comprises electroplated copper.
8 . The integrated circuit chip of claim 1 , wherein said second metallization structure comprises aluminum.
9 . The integrated circuit chip of claim 1 , wherein said second metallization structure comprises nickel.
10 . The integrated circuit chip of claim 1 , wherein said contact point comprises electroplated copper.
11 . The integrated circuit chip of claim 1 , wherein said contact point comprises aluminum.
12 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises a contact point having a size of between 0.3 and 5.0 microns;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing said contact point, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
an electroplated metal over said contact point.
13 . The integrated circuit chip of claim 12 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point.
14 . The integrated circuit chip of claim 13 , wherein said polymer layer has a thickness between 2 and 30 microns.
15 . The integrated circuit chip of claim 13 , wherein said polymer layer comprises polyimide.
16 . The integrated circuit chip of claim 13 , wherein said polymer layer comprises benzocyclobutene (BCB).
17 . The integrated circuit chip of claim 12 , wherein said contact point comprises electroplated copper.
18 . The integrated circuit chip of claim 12 , wherein said contact point comprises aluminum.
19 . The integrated circuit chip of claim 12 , wherein said electroplated metal comprises copper.
20 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a first contact point having a size of between 0.3 and 5.0 microns and a second contact point;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing said first contact point, and a second opening in said passivation layer exposing a second contact point, wherein said first and second contact points are separated from each other, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a second metallization structure over said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure.
21 . The integrated circuit chip of claim 20 further comprising a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point, and wherein said second metallization structure is over said polymer layer.
22 . The integrated circuit chip of claim 21 , wherein said polymer layer has a thickness between 2 and 30 microns.
23 . The integrated circuit chip of claim 21 , wherein said polymer layer comprises polyimide.
24 . The integrated circuit chip of claim 21 , wherein said polymer layer comprises benzocyclobutene (BCB).
25 . The integrated circuit chip of claim 20 , wherein said second metallization structure comprises electroplated copper.
26 . The integrated circuit chip of claim 20 , wherein said second metallization structure comprises aluminum.
27 . The integrated circuit chip of claim 20 , wherein said second metallization structure comprises nickel.
28 . The integrated circuit chip of claim 20 , wherein said second metallization structure comprises an electroless metal.
29 . The integrated circuit chip of claim 20 , wherein said first contact point comprises electroplated copper.
30 . The integrated circuit chip of claim 20 , wherein said first contact point comprises aluminum.