Isolation trench processing for strain control
View Patent ↗A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures may be formed, e.g., by epitaxy, on sidewalls of the trench. The structures may be silicon or a silicon compound, e.g., silicon germanium. During the thermal oxidation, the semiconductor structures are consumed. In the case of a silicon germanium, the germanium may diffuse during the thermal oxidation to produce a silicon germanium channel region.
1. A semiconductor fabrication process, comprising:
forming a hard mask overlying an active layer of a wafer, the active layer overlying a buried oxide layer;
removing a portion of the hard mask and the active layer to form a trench in the active layer, the trench extending through the active layer to the oxide layer wherein active layer portions of sidewalls of the trench expose portions of the active layer and buried oxide portions of the sidewalls expose portions of the buried oxide layer;
forming semiconductor structures selectively on the active layer portions of the trench sidewalls without forming the semiconductor structures directly on the buried oxide portions of the sidewalls; and
forming an isolation dielectric in the trench.
2. The method of claim 1 , wherein forming the hard mask includes forming a silicon nitride layer overlying the active layer.
3. The method of claim 1 , wherein the active layer includes a silicon layer and wherein forming the isolation dielectric includes exposing the wafer to an oxygen bearing ambient maintained at a temperature exceeding 600°C.
4. The method of claim 1 , wherein the buried oxide layer overlies a bulk layer of the wafer.
5. The method of claim 1 , wherein the semiconductor structures include silicon.
6. The method of claim 5 , wherein forming the semiconductors comprises forming the semiconductor structures by epitaxy.
7. The method of claim 6 , wherein the active layer includes silicon.
8. The method of claim 6 , wherein forming the semiconductor structures by epitaxy comprises forming the semiconductor structures by heteroepitaxy.
9. The method of claim 8 , wherein the active layer is silicon and the semiconductor structures comprise a compound semiconductor.
10. The method of claim 9 , wherein the semiconductor structures comprise silicon germanium.
11. The method of claim 5 , wherein forming the isolation dielectric is performed for a duration sufficient to consume the semiconductor structures completely.
12. A semiconductor fabrication process for forming isolation structures, comprising:
forming a hard mask layer overlying an active layer of a wafer; and
forming a trench in a PMOS region of the active layer, wherein forming the trench comprises removing at least a portion of the PMOS region and portions of the hard mask layer overlying the portion of the PMOS region;
forming a semiconductor structure on a sidewall portion of the trench without forming the semiconductor structure directly on a lower surface of the trench;
forming a compressive dielectric in the trench wherein the dielectric exerts compressive strain on a channel region laterally adjacent to the compressive dielectric.
13. The method of claim 12 , wherein the hard mask layer comprises silicon nitride.
14. The method of claim 12 , wherein forming the compressive dielectric comprises growing the compressive dielectric by thermal oxidation.
15. The method of claim 12 , wherein forming the semiconductor structure comprises forming the semiconductor structure epitaxially wherein the semiconductor structure and the active layer share a common crystal lattice.
16. The method of claim 12 , wherein the semiconductor structure comprises a material selected from the group consisting of silicon carbon and silicon germanium.
17. A semiconductor fabrication method, comprising:
forming a trench in an upper portion of a wafer, the trench having sidewalls including active layer portions exposing portions of an active layer and buried oxide portions exposing portions of a buried oxide layer underlying the active layer;
forming epitaxial structures selectively on the active layer portions of the sidewalls without forming the epitaxial structures directly on the buried oxide portions of the sidewalls; and
forming a compressive dielectric by thermal oxidation in the trench wherein the thermal oxidation at least partially consumes the epitaxial structures.
18. The method of claim 17 , wherein the upper portion of the wafer comprises silicon and wherein forming the epitaxial structures comprises forming structures of a material selected from silicon, silicon carbon, and silicon germanium.