NAND flash memory and data programming method thereof

1. A semiconductor integrated circuit device comprising:

even-numbered bit lines;

odd-numbered bit lines;

cell source lines;

first memory elements electrically connected between the even-numbered bit lines and the cell source lines; and

second memory elements electrically connected between the odd-numbered bit lines and the cell source lines and belonging to the same rows as the first memory elements;

wherein a potential corresponding to data to be programmed is applied to the first memory element via the even-numbered bit line and a potential which suppresses programming is applied to the second memory element via the cell source line while the odd-numbered bit lines are kept in an electrically floating state when data is programmed into the first memory element, and a potential corresponding to data to be programmed is applied to the second memory element via the odd-numbered bit line and a potential which suppresses programming is applied to the first memory element via the cell source line while the even-numbered bit lines are kept in an electrically floating state when data is programmed into the second memory element.

2. The device according to claim 1 , wherein the first memory element is a first NAND string, the second memory element is a second NAND string, the first NAND string includes a first bit line-side selection transistor, a first cell source line-side selection transistor and at least one first memory cell transistor serially connected between one end of a current path of the first bit line-side selection transistor and one end of a current path of the first cell source line-side selection transistor, the second NAND string includes a second bit line-side selection transistor, a second cell source line-side selection transistor and at least one second memory cell transistor serially connected between one end of a current path of the second bit line-side selection transistor and one end of a current path of the second cell source line-side selection transistor, the first bit line-side selection transistor and second cell source line-side selection transistor are driven by a first common selection gate signal, the first cell source line-side selection transistor and second bit line-side selection transistor are driven by a second common selection gate signal, and the first and second memory cell transistors are driven by a common row selection signal.

3. The device according to claim 2 , wherein the cell source lines contain even-numbered cell source lines and odd-numbered cell source lines, the first bit line-side selection transistors are arranged on the same row as the second cell source line-side selection transistors, the first cell source line-side selection transistors are arranged on the same row as the second bit line-side selection transistors, and the first memory cell transistors are arranged on the same row as the second memory cell transistors.

4. The device according to claim 3 , wherein the even-numbered cell source lines and odd-numbered cell source lines intersect the even-numbered bit lines and odd-numbered bit lines.

5. The device according to claim 4 , wherein the even-numbered bit lines and odd-numbered bit lines are arranged above the even-numbered cell source lines and odd-numbered cell source lines.

6. The device according to claim 5 , wherein the other end of the current path of each of the first bit line-side selection transistors is electrically connected to a corresponding one of even-numbered local internal wirings via a first plug, the even-numbered local internal wiring is electrically connected to the even-numbered bit line via a second plug, the other end of the current path of each of the second cell source line-side selection transistors is electrically connected to a corresponding one of the odd-numbered cell source lines via a third plug, the other end of the current path of each of the second bit line-side selection transistors is electrically connected to a corresponding one of odd-numbered local internal wirings via a fourth plug, the odd-numbered local internal wiring is electrically connected to the odd-numbered bit line via a fifth plug, and the other end of the current path of each of the first cell source line-side selection transistors is electrically connected to a corresponding one of the even-numbered cell source lines via a sixth plug.

7. The device according to claim 6 , wherein the even-numbered cell source lines and odd-numbered cell source lines are arranged on the same plane as the even-numbered local internal wirings and odd-numbered local internal wirings, the odd-numbered cell source line includes an odd-numbered in-bit local portion extending in a direction parallel to the even-numbered local internal wirings and an odd-numbered bit-common portion extending in a direction which intersects the even-numbered local internal wirings, and the even-numbered cell source line includes an even-numbered in-bit local portion extending in a direction parallel to the odd-numbered local internal wirings and an even-numbered bit-common portion extending in a direction which intersects the odd-numbered local internal wirings.

8. The device according to claim 7 , wherein the even-numbered bit-common portion and odd-numbered bit-common portion have mesh-form opening patterns.

9. The device according to claim 7 , wherein the odd-numbered bit-common portions are arranged above the first and second memory cell transistors.

10. A semiconductor integrated circuit device comprising:

even-numbered bit lines;

odd-numbered bit lines;

a page buffer;

a first selection switch circuit which selectively electrically connects the page buffer to one of the even-numbered bit lines and odd-numbered bit lines;

a second selection switch circuit which sets one of the even-numbered bit lines and odd-numbered bit lines into an electrically floating state;

cell source lines;

a cell source line driving circuit which drives the cell source lines by use of different potentials at programming time and read time;

first memory elements connected between the even-numbered bit lines and the cell source lines; and

second memory elements connected between the odd-numbered bit lines and the cell source lines and belonging to the same rows as the first memory elements.

11. The device according to claim 10 , wherein the first memory element is a first NAND string, the second memory element is a second NAND string, the first NAND string includes a first bit line-side selection transistor, a first cell source line-side selection transistor and at least one first memory cell transistor serially connected between one end of a current path of the first bit line-side selection transistor and one end of a current path of the first cell source line-side selection transistor, the second NAND string includes a second bit line-side selection transistor, a second cell source line-side selection transistor and at least one second memory cell transistor serially connected between one end of a current path of the second bit line-side selection transistor and one end of a current path of the second cell source line-side selection transistor, the first bit line-side selection transistor and second cell source line-side selection transistor are driven by a first common selection gate signal, the first cell source line-side selection transistor and second bit line-side selection transistor are driven by a second common selection gate signal, and the first and second memory cell transistors are driven by a common row selection signal.

12. The device according to claim 11 , wherein the cell source lines contain even-numbered cell source lines and odd-numbered cell source lines, the first bit line-side selection transistors are arranged on the same row as the second cell source line-side selection transistors, the first cell source line-side selection transistors are arranged on the same row as the second bit line-side selection transistors, and the first memory cell transistors are arranged on the same row as the second memory cell transistors.

13. The device according to claim 12 , wherein the even-numbered cell source lines and odd-numbered cell source lines intersect the even-numbered bit lines and odd-numbered bit lines.

14. The device according to claim 13 , wherein the even-numbered bit lines and odd-numbered bit lines are arranged above the even-numbered cell source lines and odd-numbered cell source lines.

15. The device according to claim 14 , wherein the other end of the current path of each of the first bit line-side selection transistors is electrically connected to a corresponding one of even-numbered local internal wirings via a first plug, the even-numbered local internal wiring is electrically connected to the even-numbered bit line via a second plug, the other end of the current path of each of the second cell source line-side selection transistors is electrically connected to a corresponding one of the odd-numbered cell source lines via a third plug, the other end of the current path of each of the second bit line-side selection transistors is electrically connected to a corresponding one of odd-numbered local internal wirings via a fourth plug, the odd-numbered local internal wiring is electrically connected to the odd-numbered bit line via a fifth plug, and the other end of the current path of each of the first cell source line-side selection transistors is electrically connected to a corresponding one of the even-numbered cell source lines via a sixth plug.

16. The device according to claim 15 , wherein the even-numbered cell source lines and odd-numbered cell source lines are arranged on the same plane as the even-numbered local internal wirings and odd-numbered local internal wirings, the odd-numbered cell source line includes an odd-numbered in-bit local portion extending in a direction parallel to the even-numbered local internal wirings and an odd-numbered bit-common portion extending in a direction which intersects the even-numbered local internal wirings, and the even-numbered cell source line includes an even-numbered in-bit local portion extending in a direction parallel to the odd-numbered local internal wirings and an even-numbered bit-common portion extending in a direction which intersects the odd-numbered local internal wirings.

17. The device according to claim 16 , wherein the even-numbered bit-common portion and odd-numbered bit-common portion have mesh-form opening patterns.

18. The device according to claim 16 , wherein the odd-numbered bit-common portions are arranged above the first and second memory cell transistors.

19. A data programming method for a semiconductor integrated circuit device which includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit lines and the cell source lines, and second memory elements electrically connected between the odd-numbered bit lines and the cell source lines and belonging to the same rows as the first memory elements, comprising:

applying a potential corresponding to data to be programmed to the first memory element via the even-numbered bit line and applying a potential which suppresses programming to the second memory element via the cell source line while the odd-numbered bit lines are kept in an electrically floating state when data is programmed into the first memory element, and

applying a potential corresponding to data to be programmed to the second memory element via the odd-numbered bit line and applying a potential which suppresses programming to the first memory element via the cell source line while the even-numbered bit lines are kept in an electrically floating state when data is programmed into the second memory element.

20. The data programming method according to claim 19 , wherein the first memory element is a first NAND string, the second memory element is a second NAND string, the first NAND string includes a first bit line-side selection transistor, a first cell source line-side selection transistor and at least one first memory cell transistor serially connected between one end of a current path of the first bit line-side selection transistor and one end of a current path of the first cell source line-side selection transistor, the second NAND string includes a second bit line-side selection transistor, a second cell source line-side selection transistor and at least one second memory cell transistor serially connected between one end of a current path of the second bit line-side selection transistor and one end of a current path of the second cell source line-side selection transistor, the first bit line-side selection transistor and second cell source line-side selection transistor are driven by a first common selection gate signal, the first cell source line-side selection transistor and second bit line-side selection transistor are driven by a second common selection gate signal, and the first and second memory cell transistors are driven by a common row selection signal.