CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER

1 . A method of forming a conductive element for an integrated circuit (IC) chip, the method comprising:

providing a device layer of the IC chip;

forming a first sacrificial layer over the device layer;

forming a first patterned mask on the first sacrificial layer having a pattern for a first dielectric layer to surround the conductive element;

etching to pattern the first sacrificial layer using the first patterned mask;

forming the first dielectric layer within the patterned first sacrificial layer;

removing the patterned first sacrificial layer, leaving the first dielectric layer; and

forming the conductive element in a space vacated by the patterned first sacrificial layer.

2 . The method of claim 1 , wherein the first sacrificial layer is selected from the group consisting of: silicon dioxide (SiO 2 ), germano-silicate glass and germanium (Ge).

3 . The method of claim 1 , wherein the first sacrificial layer forming includes one of: spin applying the first sacrificial layer and baking, and vapor depositing the first sacrificial layer and annealing.

4 . The method of claim 1 , wherein in the case that the first sacrificial layer includes silicon dioxide (SiO 2 ) or germano-silicate glass, the removing includes using a dilute hydrofluoric (HF) acid.

5 . The method of claim 1 , wherein in the case that the first sacrificial layer includes germanium (Ge), the removing includes using a hydrogen peroxide (H 2 O 2 ) solution.

6 . The method of claim 1 , wherein the patterned mask forming includes: forming a photoresist, patterning the photoresist with a mask and exposure tool, etching the photoresist, and stripping un-exposed photoresist.

7 . The method of claim 1 , wherein the first dielectric layer forming includes:

one of: spin applying, and vapor depositing the first dielectric layer;

annealing; and

planarizing.

8 . The method of claim 1 , wherein the conductive element forming includes: depositing a liner, depositing a metal, and planarizing.

9 . The method of claim 8 , wherein the liner is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta) and ruthenium (Ru).

10 . The method of claim 1 , wherein the conductive element includes one of a laterally extending wire and a via.

11 . The method of claim 1 , wherein in the case that the conductive element includes a via and a laterally extending wire, the patterned first sacrificial layer is patterned for the via of the conductive element, further comprising prior to the patterned first sacrificial layer removing:

forming an etch stop layer over the patterned first sacrificial layer and the first dielectric layer;

forming a second sacrificial layer over the first sacrificial layer and the first dielectric layer;

forming a second patterned mask on the second sacrificial layer having a pattern for a second dielectric layer to surround the wire of the conductive element;

etching to pattern the second sacrificial layer using the second patterned mask;

forming the second dielectric layer within the patterned second sacrificial layer; and

removing the patterned second sacrificial layer; and

removing the etch stop layer,

wherein the conductive element forming further includes forming the conductive element in a space vacated by the patterned second sacrificial layer.

12 . A structure comprising:

a conductive element positioned within a dielectric layer,

wherein the dielectric layer is free of damage at an edge thereof adjacent to the conductive element.

13 . The structure of claim 12 , wherein the conductive element includes at least one of: a laterally extending wire or a via.

14 . A method of forming a conductive element for an integrated circuit (IC) chip, the method comprising:

forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element;

forming the first dielectric layer within the patterned first sacrificial layer;

removing the patterned first sacrificial layer, leaving the first dielectric layer; and

forming the conductive element in a space vacated by the patterned first sacrificial layer.

15 . The method of claim 14 , wherein the conductive element includes one of a laterally extending wire and a via.

16 . The method of claim 14 , wherein in the case that the conductive element includes a via and a laterally extending wire, the patterned first sacrificial layer is patterned for the via of the conductive element, further comprising prior to the patterned first sacrificial layer removing:

forming an etch stop layer over the patterned first sacrificial layer and the first dielectric layer;

forming a second sacrificial layer having a pattern therein for a second dielectric layer to surround a wire of the conductive element;

forming the second dielectric layer within the patterned second sacrificial layer; and

removing the patterned second sacrificial layer; and

removing the etch stop layer,

wherein the conductive element forming further includes forming the conductive element in a space vacated by the patterned second sacrificial layer.

17 . The method of claim 16 , wherein the first and second sacrificial layer are selected from the group consisting of: silicon dioxide (SiO 2 ), germano-silicate glass and germanium (Ge).

18 . The method of claim 16 , wherein the first and second sacrificial layer forming each include one of: a) spin applying the first sacrificial layer and baking, and b) vapor depositing the first sacrificial layer and annealing.

19 . The method of claim 16 , wherein in the case that the first sacrificial layer or the second sacrificial layer includes silicon dioxide (SiO 2 ) or germano-silicate glass, a respective removing includes using a dilute hydrofluoric (HF) acid.

20 . The method of claim 16 , wherein in the case that the first sacrificial layer or the second sacrificial layer includes germanium (Ge), a respective removing includes using a hydrogen peroxide (H 2 O 2 ) solution.