Semiconductor device and semiconductor wafer and a method for manufacturing the same
View Patent ↗The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10 . The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22 . The semiconductor substrate 22 , which is an SOI substrate, is constituted by comprising an insulating layer 34 , and a silicon layer 36 , which is provided on the insulating layer 34 , including a circuit forming region A 1 . The insulating layer 34 functions as a protective film (a first protective film) covering a lower face (a face opposite to the semiconductor chip 10 ) of the circuit forming region A 1 . A protective film 38 (a second protective film) is provided on the semiconductor substrate 22 . The protective film 38 covers a side face of the circuit forming region A 1.
1. A semiconductor device comprising:
a first semiconductor chip;
a second semiconductor chip, which has a semiconductor substrate including a circuit forming region, formed on said first semiconductor chip,
wherein said second semiconductor chip has a first protective film covering a face opposite to said first semiconductor chip in said circuit forming region and has a second protective film covering an outer side face of said circuit forming region; and
a through electrode penetrating from a first side surface of said first protective film through a second side surface of said first protective film and said circuit forming region,
wherein an area of said first semiconductor chip is larger than an area of said second semiconductor chip and wherein said second semiconductor chip includes a plurality of conductors penetrating through said first protective film and said circuit forming region and contacting an interconnect layer that directly connects another interconnect layer on said first semiconductor chip.
2. The semiconductor device according to claim 1 , wherein an area of said first semiconductor chip is larger than an area of said second semiconductor chip.
3. The semiconductor device according to claim 1 , wherein said semiconductor substrate is constituted by comprising an insulating layer functioning as said first protective film, and a silicon layer, which is provided on said insulating layer, including said circuit forming region, and wherein said insulating layer is exposed on a face opposite to said first semiconductor chip in said second semiconductor chip.
4. The semiconductor device according to claim 1 , wherein said second semiconductor chip has an interconnect layer at a lower part of said circuit forming region, and wherein a third protective film is provided so as to cover said interconnect layer.
5. The semiconductor device according to claim 1 , wherein said second semiconductor chip includes a conductor penetrating said semiconductor substrate in said circuit forming region.
6. The semiconductor device according to claim 5 , wherein said semiconductor device includes a third semiconductor chip formed on said second semiconductor chip, and wherein said second semiconductor chip is electrically connected to said third semiconductor chip via said conductor.
7. The semiconductor device according to claim 1 , wherein said circuit forming region is surrounded by said second protective film.
8. A semiconductor wafer comprising:
a base wafer;
a semiconductor chip, which has a semiconductor substrate including a circuit forming region, formed on said base wafer,
wherein said semiconductor chip has a first protective film covering a face opposite to said base wafer in said circuit forming region and has a second protective film covering an outer side face of said circuit forming region; and
a through electrode penetrating from a first side surface of said first protective film through a second side surface of said first protective film and said circuit forming,
wherein an area of said base wafer is larger than an area of said semiconductor chip and wherein said semiconductor chip includes a plurality of conductors penetrating through said first protective film and said circuit forming region and contacting an interconnect layer that directly connects another interconnect layer on said base wafer.
9. The semiconductor wafer according to claim 8 , wherein a plurality of said semiconductor chips are provided on said base wafer at a predetermined interval.
10. The semiconductor wafer according to claim 8 , wherein said semiconductor chip has an interconnect layer at a lower part of said circuit forming region, and wherein there is provided a third protective film is provided so as to cover said interconnect layer.
11. The semiconductor wafer according to claim 8 , wherein said semiconductor chip includes a conductor penetrating a semiconductor substrate in said circuit forming region.
12. The semiconductor wafer according to claim 11 , wherein said semiconductor wafer includes an upper part semiconductor chip formed on said semiconductor chip, and wherein said semiconductor chip is electrically connected to said upper part semiconductor chip via said conductor.
13. A semiconductor device comprising:
a first semiconductor chip;
a second semiconductor chip, which has a semiconductor substrate including a circuit forming region, formed on said first semiconductor chip,
wherein said second semiconductor chip has a first protective film covering a face opposite to said first semiconductor chip in said circuit forming region and has a second protective film covering a side face at an outer periphery of said circuit forming region; and
a through electrode penetrating from a first side surface of said first protective film through a second side surface of said first protective film and said circuit forming region,
wherein an area of said first semiconductor chip is larger than an area of said second semiconductor chip and wherein said second semiconductor chip includes a plurality of conductors penetrating through said first protective film and said circuit forming region and contacting an interconnect layer that directly connects another interconnect layer on said first semiconductor chip.