Power amplifier circuit having a bias signal inputted into input terminal and method thereof
The present invention discloses an adjustable gain power amplifier circuit. The adjustable gain power amplifier circuit includes a power amplifying unit for receiving and amplifying an input signal to generate an output signal; a power detecting unit for detecting power of the input signal to generate a detecting signal; and a biasing control unit for generating a biasing signal according to the detecting signal and to output the biasing signal.
1. An adjustable gain power amplifier circuit, comprising:
a power amplifying unit, for receiving an input signal and amplifying the input signal to generate an output signal;
a power detecting unit, for detecting power of the input signal to generate a detecting signal, wherein the power detecting unit comprises:
a capacitor, having a first terminal coupled to an input terminal of the power amplifying unit, for eliminating a DC component of the input signal to generate an AC component of the input signal; and
a first transistor, having a gate terminal coupled to a second terminal of the capacitor, for amplifying the AC component of the input signal to generate the detecting signal; and
a biasing control unit, for generating a biasing signal according to the detecting signal and outputting the biasing signal.
2. The power amplifier circuit of claim 1 , wherein the biasing control unit comprises:
two transistors configured to act as a current mirror;
a diode-connected transistor, coupled to the current mirror; and
an inductor, having a terminal directly connected to a drain terminal of the diode-connected transistor.
3. The power amplifier circuit of claim 1 , wherein the biasing control unit outputs the biasing signal to an input terminal of the power amplifying unit, the biasing control unit comprises:
two transistors configured to act as a current mirror;
a diode-connected transistor, coupled to the current mirror; and
a resistor, having a first terminal coupled to a drain terminal of the diode-connected transistor and a second terminal outputting the biasing signal.
4. The power amplifier circuit of claim 1 , wherein the biasing control unit outputs the biasing signal to the power amplifying unit.
5. The power amplifier circuit of claim 1 , wherein the power detecting unit is an envelope detector.
6. The power amplifier circuit of claim 1 , further comprising a matching device, for matching the power amplifying unit.
7. An adjustable gain power amplifier circuit, comprising:
a power amplifying unit, for receiving an input signal and amplifying the input signal to generate an output signal;
a power detecting unit, coupled to an output terminal of the power amplifying unit, for detecting power of the output signal to generate a detecting signal; and
a biasing control unit, coupled to an input terminal of the power amplifying unit, for generating a biasing signal according to the detecting signal and outputting the biasing signal to the input terminal of the power amplifying unit;
wherein the biasing control unit comprises:
a power level adjusting unit, coupled to the power detecting unit, for adjusting the detecting signal to generate an adjusted detecting signal;
a buffering unit, coupled to the power level adjusting unit, for receiving the adjusted detecting signal;
two transistors configured to act as a current mirror, having a first terminal coupled to the buffering unit;
a diode-connected transistor, having a gate terminal coupled to a second terminal of the current mirror; and
an inductor, having a first terminal coupled to a drain terminal of the diode-connected transistor, and a second terminal outputted the biasing signal to the input terminal of the power amplifying unit.
8. The power amplifier circuit of claim 7 , wherein the power detecting unit comprises:
a first transistor, having a gate terminal coupled to the output terminal of the power amplifying unit, and a drain terminal outputted the detecting signal.
9. The power amplifier circuit of claim 7 , wherein the power detecting unit is an envelope detector.
10. The power amplifier circuit of claim 7 , further comprising a matching device, for matching the power amplifying unit.
11. An adjustable gain power amplifier circuit, comprising:
a power amplifying unit, for receiving an input signal and amplifying the input signal to generate an output signal;
a power detecting unit, coupled to an output terminal of the power amplifying unit, for detecting power of the output signal to generate a detecting signal; and
a biasing control unit, coupled to an input terminal of the power amplifying unit, for generating a biasing signal according to the detecting signal and outputting the biasing signal to the input terminal of the power amplifying unit;
wherein the biasing control unit comprises:
a power level adjusting unit, coupled to the power detecting unit, for adjusting the detecting signal to generate an adjusted detecting signal;
a buffering unit, coupled to the power level adjusting unit, for receiving the adjusted detecting signal;
two transistors configured to act as a current mirror, having a first terminal coupled to the buffering unit;
a diode-connected transistor, having a gate terminal coupled to a second terminal of the current mirror; and
a resistor, having a first terminal coupled to a drain terminal of the diode-connected transistor, and a second terminal outputted the biasing signal to the input terminal of the power amplifying unit.
12. The power amplifier circuit of claim 11 , wherein the power detecting unit comprises:
a first transistor, having a gate terminal coupled to the output terminal of the power amplifying unit, and a drain terminal outputted the detecting signal.
13. The power amplifier circuit of claim 11 , wherein the power detecting unit is an envelope detector.
14. The power amplifier circuit of claim 11 , further comprising a matching device, for matching the power amplifying unit.